HDL IFFT optimize latency
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sameer al-obaidi
am 5 Dez. 2015
Kommentiert: Bharath Venkataraman
am 5 Jan. 2016
Hi; I used Optimize HDL IFFT but i have latency delay in the output which a lot of zero i think it is the like a time delay of real time processing. My question is how can i remove this zero in the output
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Bharath Venkataraman
am 7 Dez. 2015
Bearbeitet: Bharath Venkataraman
am 7 Dez. 2015
The latency indicates the real-life behavior of the system on an FPGA or ASIC. To look at the data only when it is valid, use the valid output of the block and look at the data only when the validOut is high.
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Bharath Venkataraman
am 5 Jan. 2016
For your purposes, I believe you should take the output of the IFFT, and send it to a To Workspace block along with the validOut. In MATLAB, you can look at the data for all the indices which have validOut high. If the To Workspace output variables are dataOut and validOut, dataOut(validOut) -> should give you all the data when validOut is high.
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