generated HDL code failing in cadence AMS

I am working with with Simulink on design of a AGC (automatic gain control) and generated HDL code for the same successfully. Cosimulation using vivado simulator was also successful.

But when we integrated the model into Cadence AMS, its not working as we intended. Basic idea of AGC is to control the VGA with 20 levels of gain steps but in cadence we only getting the top and bottom levels of gain steps. (not intermediate ones). So my doubt is will using the rate transition block in simulink model fails to work in Cadence or not.?

Answer 1

[Kiran Kintali]

https://www.mathworks.com/help/hdlcoder/index.html

HDL Coder generates Synthesizable RTL.

For the list of supported blocks in R2025b see this list

For Rate Transition block related information you can visit this page and scroll down to Extended Capabilities: HDL Code Generation.

Feel free to reach out to tech support for additional help.