HDL Coder Error when converting AXI4 interface with different data rates

I'm having trouble understanding this error from HDL coder:

Failed All the DUT ports connecting to the "f2h_sdram0 Read" interface must be running at the fastest rate in the generated DUT HDL code. Port "data_in" uses sample rate of 5e-06, the fastest rate in the DUT HDL code is 2e-07.

Error using hdlturnkey.data.Channel/validateCodeGenPortRate

All the DUT ports connecting to the "f2h_sdram0 Read" interface must be running at the fastest rate in the generated DUT HDL code. Port

"data_in" uses sample rate of 5e-06, the fastest rate in the DUT HDL code is 2e-07.

I want to read from a particular address in memory every 5 us. I don't want to read every 2e-7 seconds and flood the bus with uneeded read requests. I tried checking the timing legend and nothing even seems to be running at 2e-07 so i'm not sure where it is getting that rate from in the first place.

Am i approaching the sampling logic for this incorrectly? Instead of controlling when it performs a read by changing the execution time of the read-slave-to-master interface and Data signals, should i let the execution time be set to -1 (inherited) and control the read time by changing the rd_dvalid signal using temporal logic in my stateflow chart? Thanks for any help.

Answer 1

[Wang Chen]

Hi John,

From the error message, it looks like you are using the "AXI4 Master" interface.

HDL Coder currently requires the DUT ports that map to the AXI4 Master interface run at the fastest rate of the design after HDL code generation. Please see following documentation for details:

https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-master-interface-generation.html#mw_afa2aed2-076c-4724-81e4-402b091c6c54

Your understanding is correct: "Instead of controlling when it performs a read by changing the execution time of the read-slave-to-master interface and Data signals, should i let the execution time be set to -1 (inherited) and control the read time by changing the rd_dvalid signal using temporal logic in my stateflow chart? "

The DUT port and logic that mapped to AXI4 Master interfaces should run at the fastest rate in the DUT. The AXI protocol signals like rd_avalid should be used to control the read/write operation, so you can control the frequency of the read/write using these signals. The full protocol is defined in this document:

https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-master-interface-generation.html#mw_3732d6ab-cb87-443a-add1-3392e0b7c9e2

You can also refer to this example model where we perform both read/write DDR access using AXI4 Master interface.

https://www.mathworks.com/help/hdlcoder/ug/performing-large-matrix-operation-on-fpga-using-external-memory.html

Please also note, to use AXI4 Master interface, we should avoid the settings that will introduce oversampling. The oversampling will make the DUT port data rate slower compared to the fastest clock of the generated HDL code.

https://www.mathworks.com/help/hdlcoder/ug/generating-a-global-oversampling-clock.html

Thanks,

Wang

[John]

ok, thanks. It looks like I had an oversampling factor set to 5. I then had to disable clock-rate pipelining. Once I changed the oversampling factor back to 1, it got rid of that 2e-7 rate that I wasn't sure where it was coming from. I then based the sample time of the AXI4 RAM interface off of the fastest rate and that seemed to work. I can then control the actual frequency of AXI4 read/write tranactions by manipulating the timing of the AXI4 handshake signals such as rd_dvalid in my FSM.