Clarifications regarding the SVPWM Generator (2-Level) block

Hello,

I’m working with the SVPWM Generator (2-Level) block, but I’m getting the warning shown in the attached image. Should the Alpha–Beta inputs be normalized with respect to the DC link? I’ve tried doing so, but the message still appears. My simulation is discrete, with a sample time of 2e-6.

Best regards,

Fabián

[Sabin]

Would be helpful to attach a model where the problem can be reproduced.