Implementing parallel processing and handling sampling vs. clock rate differences in an OFDM system using Simulink, HDL Coder, AXI Interface.

I’m currently working on an OFDM-based system using Simulink + HDL Coder, targeting RFSoC using Vivado tool, and AXI Interface. I would sincerely appreciate your guidance on the following topics. Despite reviewing the documentation and trying things out in Simulink, the following three topics remain unclear:

1. Vector Processing and Parallelism with HDL Coder

My current model uses a 100 MHz sample rate. I want to scale this to at least 400 MHz. Since increasing the sample rate directly is impractical, I plan to use 4 parallel data streams instead.

Some blocks (e.g., FFT, IFFT, modulators,Dual Port Ram ) seem to support vector inputs like [4×1]. But I'm not sure if this kind of vector input, output is available in HDL coder, actually synthesizing HDL codes.

Questions:

• Does HDL Coder support synthesizable HDL codegen when passing vector signals (e.g., [4×1]) between HDL-supported blocks (like FFT/IFFT/RAMS,etc)?
• Is it possible to perform vector processing with RAMs like Dual Port RAM? When using it, if I want to apply 4x1 vector to the wr_din input, which part of the internal settings should I modify? I'm struggling with dimension-related errors, and I would appreciate your help.
• Or is HDL Coder strictly scalar-stream oriented, requiring duplication of each block for each stream?
• If I have a vector of simultaneously processed signals (generated in parallel like [4x1]), and I want to send them out through an AXI Stream interface, is it necessary to convert them from parallel to serial form(by using hdl coder blocks like serializer 1D) before streaming them out?

2. Loop Unrolling, SSR, and Serializer for Parallel Processing

I’ve read about Loop Unrolling and SSR (Super Sample Rate) or Frame based processing but I’m unsure how to apply them effectively.

Questions:

• Are these appropriate in this case? If so, how should it be applied in Simulink before HDL codegen?
• If vectors aren’t synthesizable in HDL, should we use Serializer1D to convert vector to scalar stream, then configure some kinds of parallelization settings like SamplesPerCycle = 4 or other loop unrolling, SSR settings?

Planned Architecture:

1. 4 scalar data streams through each duplicated blocks
2. Merge via Vector Concatenate -> Make it a vector processing parallel [4x1]
3. HDL coder FFT/IFFT/Dual Port RAM, etc blocks (If vector input/output processing is possible)
4. Convert to scalar stream using Serializer1D, and sending it by AXI-stream interface.

→ Would this be considered a valid HDL Coder + AXI Interface -compatible architecture?

3. Sample Rate vs. Clock Rate in HDL Coder

I’d like to clarify how Simulink and HDL Coder interpret and manage the difference between sample rate and FPGA clock rate.

Questions:

• If I set a 100 MHz sample rate in Simulink, does that mean valid samples are automatically spaced accordingly to this sample rate—regardless of internal logic?
• When targeting a 240 MHz FPGA clock(AXI clock) in HDL Workflow Advisor, does HDL Coder automatically manage the difference by using oversampling or handshaking techniques?

The reason I ask is that in LabVIEW FPGA development I previously used, we used Timed Loops to explicitly define the clock and manage data timing(sampling rate) manually via state machines and handshaking. In contrast, Simulink seems to abstract this through only setting sampling time settings. This difference has made it somewhat confusing for me to reason about timing and rate behavior in the HDL-generated design.

If any of my understanding is incorrect, I would deeply appreciate corrections or recommendations. I am committed to building a high-throughput OFDM system and your expert guidance would be invaluable.

Answer 1

[Jack]

1. HDL Coder can synthesize blocks with vector signals (like [4×1]) if the block supports it (for example, FFT/IFFT or some RAM blocks). If a block is strictly scalar, you may need to duplicate it or adjust its settings (e.g., set SamplesPerCycle) to work with vectors.
2. Loop unrolling and SSR (or frame-based processing) are valid ways to parallelize your design. If your blocks are scalar, you can convert a parallel vector into a serial stream using a Serializer1D block and then use unrolling settings (e.g., SamplesPerCycle = 4) to process multiple samples per clock cycle.
3. Simulink’s sample rate defines when outputs are computed, while the FPGA’s clock rate is higher. HDL Coder automatically inserts the necessary buffering or handshaking logic so your design runs with the specified sample time even on a faster clock.

Your proposed architecture—processing 4 parallel streams using vector-enabled blocks and then converting them to a serial stream for the AXI interface—is a valid approach.

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