Generate host interface script and Generate Simulink software interface model unable to select.

Performing LED blinking test using Versal VCK 190 board on Ubuntu 18.04 operating system and Xilinx Vivado 2020.2. While implementing the HDL Workflow Advisor, under Embedded System Integration, in generate software Interface option, Generate host interface script and Generate Simulink software interface model ckeckboxes are not getting highlighted. Please provide necessary solutions to troubleshoot the issue.

Answer 1

[Pratyush]

Hi Gaurav,

If the "Generate host interface script" and "Generate Simulink software interface model" options are not available in the HDL Workflow Advisor for the VCK190 board using Vivado 2020.2 on Ubuntu 18.04, consider the following troubleshooting steps:

1. Toolchain Setup: Ensure Vivado 2020.2 and compatible MATLAB/Simulink versions are correctly installed and licensed.
2. Licensing: Confirm you have licenses for Embedded Coder and HDL Coder in MATLAB/Simulink.
3. Board Support: Verify the VCK190 board support package is installed in both Vivado and MATLAB/Simulink.
4. Workflow Settings: Check the HDL Workflow Advisor settings for correct target platform and interface options.
5. Software Updates: Look for updates or patches for Vivado and MATLAB/Simulink.
6. Documentation: Review official documentation for setup and prerequisites.
7. Known Issues: Check for known issues on Xilinx and MathWorks websites.

These steps should help identify and resolve the issue with unavailable options in the HDL Workflow Advisor.

Answer 2

[MULI]

Hi Gaurav,

In addition to the steps mentioned by Pratyush, you can also try the following:

• Make sure to Set the path to Xilinx Vivado 2020.2 tool in your MATLAB session using the "hdlsetuptoolpath" function.

    hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', '/path/to/vivado');

• If you are generating the software interface model make sure you have installed Embedded Coder and Simulink Coder.
• Verify whether you have HDL Coder and Embedded Coder support packages for the target platform.

If you are targeting standalone FPGA boards, you cannot generate a software interface model because there is no embedded processor to run it. Instead, you can generatea host interface script and test the IP core by using the AXI Manager driver.

For more information and examples related to this topic you may refer to the following documentation link:

https://www.mathworks.com/help/releases/R2022a/hdlcoder/ug/generate-software-interface-model-to-probe-and-rapidly-prototype-the-hdl-ip-core.html