Exporting a simulink/Mathlab model as a circuit element for simulation software (Pspice/Cadence)

Hello wonderful community!

I am currently working on mathematical model of a thin-film AMR sensor. I have already created the model in MATLAB, as well as in Simulink (shown in the image below). Basically, you can think of it as a black box with several floating-point inputs (representing various properties of the system) and one floating-point output (the resulting sensor signal). I was also given the task of somehow integrating this mathematical object in circuit simulation software (namely Pspice or preferably, Virtuoso) as a standalone circuit element, but I am at a loss as to how this can be done.

I have asked the Cadence team for any advice, and I was told that one possible option is to convert the model to Verilog-A, and import it that way. I am aware that I can generate Verilog code via the HDL coder app, but as I have said, I have absoloutely zero knowledge of the language, and don't really know how to implement the resulting files in Pspice/Virtuoso, so I consider this a last resort. Hence, I was sent here.

Does anybody know if it is possible to somehow directly import my model into Pspice/Virtuoso? Or any other way besides Verilog conversion...

I am very grateful for any advice on the matter!

Regards,

Andrei

Answer 1

[Joel Van Sickel]

There are a few options. I am listing them by order of cost (cheapest to most expensive)

1. You can try and utilize the co-simulation feature that pspice has with Simulink. However, this interface is owned by Cadence and if they aren't recommending it to you, it might not be a good option. https://www.pspice.com/electrical-co-simulation
2. You can generate hdl using hdl coder, but it is highly likely your model will require heavy modification to do that and have a fairly steep learning curve.
3. A tool like virtuoso should also work with DPI C. In this case, you can export your model as C code and wrap it with DPI C interface to be useful in testbenches that tools like virtuoso have. This is a non trivial process and requires hdl coder AND hdl verifier. https://www.mathworks.com/help/hdlverifier/ug/dpi-c-generation-overview.html

[Andrei Cheplakov]

Hi Joel! Thanks for taking your time to answer, really appreciate it. I actually figured out how to rebuild the model in virtuoso block by block using Verilog-a. It's not the best solution, but it works for now. I'll try and look into some of the options you provided in case I need to do something similar in the future, so thanks again for the tips and have a great day!!