- Streaming Pixel Interface
- Timing Diagram of Single Pixel Serial Interface
- Configure & Troubleshoot Blanking Intervals
Problem with pixel ctrl in Vision HDL Toolbox
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Marc
am 15 Sep. 2023
Kommentiert: Marc
am 23 Sep. 2023
When I use the dilation block I don't get any output on the vEnd in the ctrl bus. The pixel input is just a constant with logic 1 for testing. For the inputs hStart, hEND, VStart and VEnd I used counters, which count up to the image border. How do I solve this?
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Chris Maliepaard
am 21 Sep. 2023
Hi Marc,
The issue may be with frame blanking which the constant input pixel value could be masking to some extent. Take a look at the following documentation for an overview of the expected bus timing, and how to troubleshoot blanking issues:
The recommended minimum horizontal blanking interval is 2×KernelWidth, though there are some additional constraints outlined in the blanking interval configuration documentation. The recommended vertical blanking interval is at least the height of the kernel.
Please create a technical support service request at Contact Us - MATLAB & Simulink (mathworks.com) and attach your model for a proper investigation if you require any more assistance.
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