Why discrete time integrator in HDL coder simulink library behaves completely differently with different input sampling time?
2 Ansichten (letzte 30 Tage)
Ältere Kommentare anzeigen
Adeel Jamal
am 11 Mär. 2022
Bearbeitet: Omkar Sastry
am 21 Mär. 2022
I use two constant blocks one with sampling freq of 2e-7(5 Mhz) and another with 4e-7 (2.5 Mhz) followed by two same discrete time integrators (Sample time:inherited). The first one outputs zero and the second one outputs a ramp (which is the correct result)... What am I missing here?
Why 2e-7 or 5 Mhz is not working with discrete time integrator???
3 Kommentare
Omkar Sastry
am 17 Mär. 2022
Bearbeitet: Omkar Sastry
am 17 Mär. 2022
Hi Adeel,
Could you please attach the other artifacts required to simulate the model (like definition for Controller.InternalSignals.DataType.PLL)? Thanks!
Akzeptierte Antwort
Adeel Jamal
am 18 Mär. 2022
Bearbeitet: Adeel Jamal
am 18 Mär. 2022
1 Kommentar
Omkar Sastry
am 21 Mär. 2022
Bearbeitet: Omkar Sastry
am 21 Mär. 2022
Hi Adeel, yes this is exactly what is happening. The 'floor' rounding mode coupled with the type used drags the value to 0 for the K*T*u(n) calculation in the first block.
Weitere Antworten (0)
Siehe auch
Kategorien
Mehr zu HDL Code Generation finden Sie in Help Center und File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!