Timing Constraint not met error for ZYNQ706

We are trying to generate bitfile for ourr simulink model for ZYNQ 706 . but encountering an error "the worst slack is -14.8ns timing constraints not met " i have optimized my simulink model as much as i can . please suggest some way to avoid this error. The error inturrupts when i increased my sampling frequency of model fro 10MHz to 20MHz. it works fine with 10MHz with out any error .

Thanks in anticipation

Answer 1

[Kiran Kintali]

You can consider pipelining the design. See the timing related optimization section in HDL Coder https://www.mathworks.com/help/hdlcoder/speed-optimization.html

Some quick tips:

1. Set some output pipelines, enable distributed pipelining.
2. Consider using adaptive pipelining for inserting pipelines next to multipliers to enable better DSP mapping
3. Use Critical Path Estimation report to see the location of the critical path in the model
4. Identify critical path and right click on the block and input and output pipelines to break the critical path, delay balancing will kick in to add matching delays