Up/Down Counter using 16-bit Kogge Stone Adder result error

We are currently running the Simulink simulation with the sampling period set to around 400ns.

The ideal output should have a straight line graph.

The problem is not at a fixed point, but at a point relative to about 60% of the total run length.

The longer the execution length, the more errors appear.

The same problem occurs even if we adjust the detailed fixed step size.

This is the Simulink figure of up/down counter we made.

'dsmout' is Delta Sigma Modulated output, which is bitstream of 0 and 1.

This is the 16-bit Kogge Stone adder's schematic.

This is pg generation schematic.

This is grey cell schematic.

This is black cell schematic.

Many thanks.

Answer 1

[Ganapathi Subramanian R]

Hello Sung,

I understand that you are building a counter with Koggle Stone Adder in Simulink and getting incorrect output during the simulation. There could be several causes for this behaviour. Here are few steps to resolve the issue.

1) If you are using a fixed-step solver, ensure that the step size is compatible with the dynamics of your system.

2) Try switching between fixed step and vaiable step solvers to see if the issue persists. Variable step solver adjusts the step size during the simulation to maintain accuracy.

3) Check for algebraic loops in your model and resolve them. This can sometime cause unexpected behaviours.