Encountered issue during FIL simulation

Good day.

Can someone help me on how to proceed in my FIL simulation because I encountered this error during simulation?

I am using Matlab R2019a version.

Regarding the SOF file, I have confirmed that I have downloaded it in the DE2-115 FPGA board.

But when I run the simulation the error above occurs.

I currently using a Straight-through LAN cable connected to a USB-to-LAN card connected to my PC.

I hope some can help or give some advice on how to fix the error.

Thank you very much!

Answer 1

[William]

Hi Gran,

Have you checked out our troubleshooting page for FIL (https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html)? Furthermore, please ensure your host NIC is configured correctly. This PID FIL demo goes through the steps for configuring the host NIC (https://www.mathworks.com/help/hdlverifier/ug/verify-hdl-implementation-of-pid-controller-using-fpga-in-the-loop.html). If you are using your own design, please try this PID FIL demo first or use use our validation tool (https://www.mathworks.com/help/hdlverifier/ug/add-custom-fpga-board-for-fpga-in-the-loop-simulation.html#btmi8fy-42). If you are using the validation UI tool please ensure you are trying this out in a clean directory so the generated files don't get clobbered with existing files in that working directory. We need to make sure we can ping the board successfully first.

If the issue persists and you need further assistance, please submit a technical support ticket.

Regards,