Failed Generated HDL code, testbench.

Hi guys.

I tried to generate my project using HDL coder. However, it failed to generate the testbench. The error is "Cannot Generate test bench code for the entire model. Please specify a simulatable subsystem in your model"

Do you know what the problem? Thanks in advance.

Answer 1

[Tim McBrayer]

HDL Coder supports generating code from a Simulink design in a few different ways. It can either generate code for a specified subsystem or for an entire model. This error message indicates that you have generated code for an entire model, and that testbench generation cannot be performed because of this.

The parts of the Simulink model outside the HDL design are referred to as the testbench; a Simulink testbench is required in order to generate a HDL testbench. Since you have no Simulink testbench, a HDL testbench cannot be created.

HDL Coder generates a testbench by running the Simulink model and capturing the inputs and outputs of the HDL subsystem that had HDL code generated for it. The HDL testbench is created using these signal values; it feeds the stored inputs to the design and verifies that the generated outputs precisely match Simulink's outputs. With no Simulink testbench to capture data from, no HDL testbench can be created.

[Anegondi Ashray Datta Pranesh]

So what is the solution for it

Answer 2

[Kiran Kintali]

The model on the left has root ports; no stimulus/source blocks in the Simulink. The model on the right has valid sources/stimulus (in this case random noise signal and valid filter coefficients). Both models generate HDL for the middle DUT block.

Generating HDL Test Bench Code from the the left model does not make sense.

makehdl(<modelName>) % should work with only root ports
makehdltb(<modelName>) % should not work and produces the error asking you to choose a subsystem

makehdl(<modelName/SubsystemName>) % should work similarly
makehdltb(<modelName/SubsystemName>) % should work technically; but apart form feeding zeros the simulation does not do much on this model; hence the generate RTL testbench is not very meaningful

Generating HDL Test Bench Code from the the right model is the recommended best practise when using HDL Coder.

makehdl(<modelName/SubsystemName>); % same as above usecase; generate RTL from the Subsystem
makehdltb(<modelName/SubsystemName>); % the model simulates with stimulus; input signals and output signals are logged and captured in the generated RTL testbench

The same reasoning applies when you choose "Generate HDL For" in the Toolstrip GUI or Worfklow Advisor and generate HDL.

Summary: Choosing model name or a subsystem name with no meaningful stimulus is not useful workflow when generating the RTL testbench using HDL Coder.