Simulink does not have Full-Precision Fixed Point Adders?!?

It does not appear that Simulink will properly produce full-precision adders. For example: If I want to add 2 signals with data types:

sfix10_En6 --> Range [-8,8), Precision 2e-6

and

ufix10_En10 --> Range [0,1), Precision 2e-10

then Simulink will propagate the output data type of an adder to be:

sfix16_En6 --> Range [-512,511), Precision 2e-6

This is satisfactory for the range, but not for the precision. In order to get full precision out of the adder, I would expect the minimal propagated type to be:

sfix15_En10 --> Range [-16,16), Precision 2e-10

This is non-intuitive. I realize that one could pad fractional bits to the first signal to "line up" the binary point prior to adding. It is not clear that this is possible to do programmatically, though, without having full access to the Fixed-Point characteristics of bit width + fraction length at compile time. I could easily query the input data types and appropriately set the output type if the binary point values were available by the API.

Does anyone know of a plan to accommodate this feature?

Thank you, -Tim Koehler

[Dara Parsavand]

Even if the binary point is in the same place, Simulink adders still do not implement a full precision adder using either Inherit via internal rule or Inherit via back propagation. E.g. with each input sfix10_En6, the output is sfix16_En6 in the former, sfix10_En6 in the latter (this is for 2012b), but it should be sfix_11_En6 . Both System Generator and Synphony work as expected when you select full precision (lining up binary point and adding a most significant bit for range growth).

Multipliers also are not full precision. E.g., here are the results for two inputs, and Inherit via internal rule (first) or Inherit via back propagation (second):

sfix_7_En4 * sfix_7_En5 = sfix16_En9, sfix7_En4

sfix_7_En4 * ufix_6_En5 = sfix16_En9, sfix7_En4

ufix_6_En4 * ufix_6_En5 = ufix16_En9, ufix6_En4

The answer I'm looking for is:

sfix14_En9

sfix13_En9

ufix12_En9

Note: In the top case, a useful answer for our group is also sfix13_En9 which is to say you don't allow two signed inputs to a multiplier to be simultaneously negative full scale.

If it were possible to use "data type expression" for the output signal attribute and form an expression using 6 parameters (fixdt(s,x,y) for each input of a pairwise adder or multiplier), that would be helpful.

Dara Parsavand

Answer 1

[Timothy Koehler]

It seems that the desired response is obtained by changing the following setting:

Model Properties --> Hardware Implementation --> Set device type to ASIC/FPGA.

Looks like I need a tutorial on all the hidden setting in the preferences menu!

[Dara Parsavand]

The path to this setting is: Simulation > Model Configuration Parameters > Hardware Implementation > Device vendor. I did not see a way to get there from File > Model Properties.

It would be useful to start from a standard template. I note that many of the hdlcoder example models, e.g.:

http://www.mathworks.com/help/hdlcoder/examples/using-multiple-clocks-in-hdl-coder.html http://www.mathworks.com/help/hdlcoder/examples/getting-started-with-ram-and-rom-in-simulink.html

do have the setting ASIC/FPGA for device vendor and type.

If you find an ideal model to start from, please let us know.

Dara