Prepare Hardware Model for Deployment

Step 3 of 6 in Target NI USRP Radios Workflow

Now that you have set up your environment for running the workflow, the next step is to prepare a Simulink^® model for your SDR algorithm.

Determine the capabilities of your radio device, such as the number of channels and the supported baseband sample rates. For details, see Determine Radio Device Capabilities.
Implement your algorithm using blocks that support HDL code generation. For more information, see Basic Guidelines for Modeling HDL Algorithm in Simulink (HDL Coder).
Use the guidelines detailed in Configure Hardware Interfaces to model the boundary of the user logic.

Determine Radio Device Capabilities

Before you start implementing your model, consider the constraints of your hardware. The capabilities of supported NI™ USRP™ radios are detailed in this table. The radio can transmit and receive at a sample rate equal to a supported master clock rate (MCR) divided by a supported interpolation or decimation factor.

Radio Device	Supported MCRs	Supported Interpolation or Decimation Factors	Number of Channels	Supported Center Frequencies	Supported Channel Gains	PL DDR Buffer Size
USRP N310	122.88 MHz 125 MHz 153.6 MHz	1, 2, or 3 Even integer in the range 4 to 256 Multiple of 4 in the range 256 to 512 Multiple of 8 in the range 512 to 1016	4	1 MHz to 6GHz Note: Only two independent center frequencies can be set, with two channels sharing the same center frequency	0 dB to 75 dB	2 GB (2²⁹ samples)
USRP N320 USRP N321	200 MHz 245.76 MHz 250 MHz	1, 2, or 3 Even integer in the range 4 to 256 Multiple of 4 in the range 256 to 512 Multiple of 8 in the range 512 to 1016	2	1 MHz to 6GHz	0 dB to 60 dB	2 GB (2²⁹ samples)
USRP X310	184.32 MHz 200 MHz	Integer in the range 1 to 128 Even integer in the range 128 to 256 Multiple of 4 in the range 256 to 512 Multiple of 8 in the range 512 to 1016	2	10 MHz to 6GHz	0 dB to 31.5 dB	1 GB (2²⁸ samples)
USRP X410	245.76 MHz 250 MHz	1, 2, or 3 Even integer in the range 4 to 256 Multiple of 4 in the range 256 to 512 Multiple of 8 in the range 512 to 1016	4	1 MHz to 8GHz	0 dB to 60 dB	4 GB (2³⁰ samples)

Configure Hardware Interfaces

NI USRP radios are software-defined radios (SDRs) that consist of a configurable radio front end and an FPGA that can perform digital functions. The diagram shows a conceptual overview of the interfaces between the internal subsystems in an NI USRP radio, and between the radio and the host.

Simplified block diagram of NI USRP radio architecture. The radio contains PL DDR buffer, user logic, and radio front end. The radio front end block connects to external transmit and receive antennas. There are streaming and register interfaces between the internal radio blocks and the host running MATLAB.

When you design your user logic, referred to as the design under test (DUT), you can include register interfaces that read and write registers in your DUT. You can also include the following data streaming interfaces:

DUT input data streaming interfaces
- From the radio front end to receive IQ data from the air
- From the host
- From the host through the PL DDR buffer
DUT output data streaming interfaces:
- To the radio front end to transmit IQ data over the air
- To the host
- To the host through the PL DDR buffer

Model your data streaming interfaces using the simplified AXI-stream protocol. For details, see Simplified AXI-Stream Protocol. Refer to the Streaming Interface Guidelines for detailed guidelines on how to configure each type of data streaming interface.

To map your DUT data streaming interfaces, see the Map Target Interfaces step of the workflow.

Register Interface Guidelines

Use register interfaces to access control registers in your DUT.

Use scalar ports only.
Use any real data type up to 32-bits.

When you deploy your design to your radio, you can read and write registers using the readPort and writePort functions.

Streaming Interface Guidelines

For HDL code generation, your Simulink model must operate using sample-based processing. Use scalar ports only in your model.

Model the streaming interfaces in your model using the simplified AXI-Stream protocol. The specific implementation of the protocol depends on the streaming interface, which are detailed in this section.

Simplified AXI-Stream Protocol. Include the following signals for each streaming data interface:

Ready — A flag that is asserted when data is ready to be received.
Data — A 32-bit bus that carries data between subsystems.
Valid — A flag that is asserted when the data is valid.
Last — A flag that is asserted for the duration of the last sample in a data packet.

Optionally, you can also include these signals:

End of burst (EOB) — A flag that is asserted for the duration of the last data packet in a burst of data packets.
Timestamp — A 64-bit signal that contains the time of the first data sample in the packet.
HasTime — A flag that is asserted when a valid timestamp signal is present.

The timing diagram shows an example of these signals with a data packet length of 4 samples and a burst length of 3 packets. Observe that samples are only sent when the receiving block indicates that it is ready to receive data by asserting the ready signal.

Timing diagram of AXI-Stream signals: data, valid, ready, and last.

Stream Data from DUT to Radio

Block diagram showing streaming interface from DUT to radio front end.

When streaming data from your DUT to the radio, configure the output IQ data, data_out, in a 32-bit bus.
- Set the port data type in your Simulink model to uint32.
- Send the quadrature (Q) component in bits <31:16>.
- Send the in-phase (I) component in bits <15:0>.
Only send data to the radio when the ready flag, ready_in, is asserted by the radio.
- The radio consumes data at the baseband sample rate, which you set using the Sample Rate configuration parameter in the Configure HDL Code Generation Settings step of the workflow, or by setting the SampleRate property on the usrp System object™.
When you receive a ready signal from the radio, send one IQ sample to the radio and assert the valid flag, valid_out.
- The DUT can send data to the radio at any rate up to the DUT clock frequency, which is configured in the Configure HDL Code Generation Settings step of the workflow. You can set this either to the highest supported MCR of the radio, or set the DUT Clock Source configuration parameter to Custom and specify a user-defined value using the Target Frequency configuration parameter.
- Send a sample every time the ready flag is asserted to avoid underflow at the transmitter.
Send IQ samples in packets of 256 samples. On the last sample of each packet, raise the last flag, last_out.
Send packets of contiguous IQ samples to the radio in bursts. On the last packet of the burst, raise the end of burst flag flag, EOB_out, for the duration of the packet. When both the last signal and end of burst signal are high, this indicates to the radio that the burst of contiguous data has ended.
You can use the timestamp signal, timestamp_out, to schedule a transmission from the radio.
- On the first packet of the burst to be transmitted, assert the HasTime signal and send a timestamp to the radio as a 64-bit unsigned integer.
- Specify the timestamp as the number of MCR clock cycles since you connected to the radio by calling setup on the usrp System object. For more information about the call sequence, see Object Functions.
- The radio only acknowledges a timestamp that is sent during the first packet in a burst.

Stream Data from Radio to DUT

Block diagram showing streaming interface from radio front end to DUT.

The radio streams IQ data, data_in, to the DUT in a 32-bit bus.
- Set the port data type in your Simulink model to uint32.
- Bits <31:16> are the quadrature (Q) component.
- Bits <15:0> are the in-phase (I) component.
When the host starts the radio front end by calling the usrp System object as a function, the radio receives IQ samples from the air at the baseband sample rate and stores them in a buffer.
- You set the baseband sample rate value using the Sample Rate configuration parameter in the Configure HDL Code Generation Settings step of the workflow, or from the host by setting the SampleRate property on the usrp System object.
- You set the stream buffer size in the Map Data Streaming Inputs step of the workflow. The default is the maximum possible buffer size.
To receive IQ samples to the DUT, assert the ready flag, ready_out.
- To ensure that the stream buffer does not overflow, request samples at a rate greater than the baseband sample rate. If the buffer overflows, the radio will stop receiving samples from the air until you start the radio front end again by calling the usrp System object as a function.
- The highest rate at which you can request samples is the DUT clock frequency, which is configured in the Configure HDL Code Generation Settings step of the workflow. You can set this either to the highest supported MCR of the radio, or set the DUT Clock Source configuration parameter to Custom and specify a user-defined value using the Target Frequency configuration parameter.
When the radio receives a ready signal from the DUT, it asserts the valid flag, valid_in, and sends one IQ sample from the stream buffer to the DUT.
The radio sends IQ samples to the DUT in packets of 256 samples. The last flag, last_in, is asserted on the final sample of each packet.
The radio sends packets of contiguous IQ samples to the DUT in bursts. The length of a burst is the number of packets required to send the data that has been requested by the DUT. For the duration of the last packet in a burst of data, the end of burst flag, EOB_in, is asserted.
The radio asserts the HasTime flag and sends a timestamp, timestamp_in, to the DUT, which is held for the duration of the packet.
- The timestamp is a 64-bit unsigned integer that contains the time at which the first sample in the packet is sent from the radio to the DUT.
- The timestamp is returned as the number of MCR clock cycles since you connected to the radio by calling setup on the usrp System object. For more information about the call sequence, see Object Functions.

Stream Data from DUT to Host

Block diagram showing streaming interface from DUT to host.

Send data, data_out, from the DUT to the host in a 32-bit bus.
- Set the port data type in your Simulink model to any data type up to 32-bits.
Only send data to the host when the ready flag, ready_in, is asserted.
- The host can receive data from the DUT when it connects to the radio by calling the setup function on the usrp System object. For more information about the call sequence, see Object Functions.
When the DUT receives a ready flag from the host, you can assert the valid flag, valid_out, and send one sample of data.
- The host buffers the data it receives in RAM.
- The host can read the data from RAM using the readPort function. The number of samples read is returned in the numSamples output argument. The overflow output argument indicates if the internal buffers overflow. If overflows occur, reduce the rate at which you send the data or use the PL DDR buffer.
Send data in packets of 256 samples. On the last sample of each packet, raise the last flag, last_out.
Send packets of contiguous data in bursts. On the last packet of each burst, raise the end of burst flag, EOB_out.

Stream Data from DUT to Host Using PL DDR Buffer

Block diagram showing streaming interface from DUT to host.

Send data, data_out, to the host through PL DDR buffer in a 32-bit bus.
- Set the port data type in your Simulink model to any data type up to 32-bits.
Send data to the PL DDR buffer when the ready flag, ready_in, is asserted.
- The PL DDR buffer asserts the ready signal when the host connects to the radio by calling setup function on the usrp System object. For more information about the call sequence, see Object Functions.
- The PL DDR buffer asserts the ready signal at the MCR. The MCR is selected based on the baseband sample rate you set using the Sample Rate configuration parameter in the Configure HDL Code Generation Settings step of the workflow, or by setting the SampleRate property on the usrp System object. You can set the baseband sample rate to any combination of a supported MCR of the radio divided by a supported interpolation factor.
  For example, if you are using a USRP N310 radio and you set the baseband sample rate to 25 MS/s, the software sets the MCR of the radio to 125 MHz and the interpolation factor to 4. In this case, the PL DDR buffer asserts the ready signal at a rate of 125 MHz.
- The PL DDR buffer de-asserts the ready signal if the buffer is full, or when the host is reading data from the buffer using the readPort function. Following a read operation, the PL DDR buffer is flushed and it is ready to receive data again.
When the DUT receives a ready flag, you can assert the valid flag, valid_out, and send one sample of data to the PL DDR buffer.
- The host reads the available data samples from the buffer using the readPort function. The number of samples read is returned in the numSamples output argument. The host reads data from the buffer with no dropped samples or overflow.
Send data in packets of 256 samples. On the last sample of each packet, raise the last flag, last_out.
Send packets of contiguous data in bursts. On the last packet of each burst, raise the end of burst flag, EOB_out.

Stream Data from Host to DUT

Block diagram showing streaming interface from host to DUT.

The host streams data, data_in, to the DUT in a 32-bit bus.
- Set the port data type in your Simulink model to any data type up to 32-bits.
When you are ready to receive data to the DUT from the host, assert the ready flag, ready_out.
- The host sends data samples to the DUT using the writePort function.
- To read data from the host asynchronously and avoid underflows, use the PL DDR buffer.
When the host receives a ready signal from the DUT during a write operation, it asserts the valid flag, valid_in, and sends one sample of data to the DUT.
The host sends data to the DUT in packets of 256 samples. The last flag, last_in, is asserted on the final sample of each packet.
The host sends packets of contiguous data to the DUT in bursts. The burst ends when the PL DDR buffer has sent all of the data specified in the writePort function. For the duration of the last packet in each burst of data, the end of burst flag, EOB_in, is asserted.

Stream Data from Host to DUT Using PL DDR Buffer

Block diagram showing streaming interface from host to DUT.

The host streams data, data_in, to the DUT through the PL DDR buffer in a 32-bit bus.
- Set the port data type in your Simulink model to any data type up to 32-bits.
When you are ready to receive data to the DUT from the host through the PL DDR buffer, assert the ready flag, ready_out.
The host sends data samples to the PL DDR buffer using the writePort function. When the PL DDR buffer receives a ready signal from the DUT after a write operation, it asserts the valid flag, valid_in, and sends one sample of data to the DUT.
- When you receive data to the DUT from the host through the PL DDR buffer, there are no dropped samples or underflows.
- When the writeMode name-value argument of the streaming interface is set to 'Once', the PL DDR buffer sends the samples to the DUT until it has sent all of the data.
- When the writeMode name-value argument of the streaming interface is set to 'Continuous', the PL DDR buffer sends the data to the DUT repeatedly.
The PL DDR buffer sends data to the DUT in packets of 256 samples. The last flag, last_in, is asserted on the final sample of each packet.
The PL DDR buffer sends packets of data to the DUT in bursts. The burst ends when:
- The host calls the release or reset function on the usrp System object. For more information about the call sequence, see Object Functions.
- The host starts a new write operation to the PL DDR buffer using the writePort function.
- The writeMode is 'Once' and the PL DDR buffer has sent all of the data specified in the writePort function.
For the duration of the last packet in a burst of data, the end of burst flag, EOB_in, is asserted.