This example shows you how to use FPGA Data Capture with existing HDL code to read FPGA internal signals. We start with an existing FPGA design that implements on-chip Analog to Digital Converter (ADC) to sample audio signal. The ADC IP exposes an Avalon Memory Mapped (MM) slave interface for control, and an Avalon streaming interface for data output. This FPGA design already contains a simple Avalon MM master to start ADC. We are going to use FPGA Data Capture feature to collect the ADC output data from the Avalon streaming interface into MATLAB workspace.
HDL Verifier Support Package for Intel FPGA Boards
Intel® Quartus Prime Software
Arrow® DECA MAX 10 FPGA development board
1. Make sure that the power switch remains OFF.
2. Connect the JTAG download cable between the FPGA development board and the host computer.
3. (Optional) Connect the line-in port of the FPGA board with an audio source, such as your cellphone, via 3.5 mm audio cable. If you skip this step, the captured data will be random noises.
Set up a working folder and provide MATLAB with access to your FPGA design software.
1. Create a folder outside the scope of your MATLAB installation folder into which you can copy the example files. The folder must be writable. This example assumes that the folder is located at C:\MyTests.
2. Start MATLAB and set the current directory in MATLAB to the folder you just created. For example:
3. To copy the example FPGA design files into your working directory, enter this MATLAB command:
4. Set up Intel Quartus. Here, we assume that the Intel Quartus executable is located in C:\altera\18.0\quartus\bin\quartus.exe. If the location of your executable is different, use your path instead.
hdlsetuptoolpath('ToolName','Altera Quartus II','ToolPath','C:\altera\18.0\quartus\bin\quartus.exe');
At the MATLAB command prompt, enter:
This command launches a graphical user interface (GUI). This example monitors two signals from the existing HDL code for the audio system. The signals are a 12-bit "adc_out", and 8-bit "counter". The "adc_out" is the digital samples of the audio line-in signal. The next signal "counter" is an 8-bit free-running counter. To configure the data capture components to operate on these two signals, make the following changes:
1. Add one row to the Ports table by clicking the "Add" button once.
2. Name the first signal to "adc_out", and the second signal to "counter".
3. Change the bit widths of the two signals to 12, and 8, respectively.
4. Make sure the FPGA vendor is set to Altera.
5. Ensure the selected language is Verilog.
6. Keep the Sample depth at 1024. This is the number of samples of each signal that the data capture tool returns to MATLAB each time a trigger is detected.
The GUI now looks like this:
Finally, click the "Generate" button to generate FPGA Data Capture component. You should see a report that confirms the generation was successful.
You must include the generated HDL IP core into the example FPGA design. You can copy the module instance code from the generated report. In this example, we are going to connect the generated HDL IP with the ADC output, and the 8-bit free-running counter.
Open the top.v file provided with this example. Add the following code immediately above the last line (endmodule) of that file.
datacapture u0 ( .clk(adc_clk), .clk_enable(adc_valid), .ready_to_capture(), .adc_out(adc_out), .counter(counter[7:0]));
We also placed above code in top.v file but commented it out. You can also uncomment that piece of code instead of adding it.
Save top.v, compile the modified FPGA design, and create an FPGA programming file by using the following tcl script.
system('quartus_sh -t adc_deca_max10.tcl &')
The tcl scripts included in this example perform these steps:
1. Create a new Quartus project.
2. Add example HDL files and the generated FPGA Data Capture HDL files to the project.
3. Compile the design.
4. Program the FPGA.
Wait until the Quartus process successfully finishes before going to the next step. This process takes approximately 5 to 10 minutes.
First, go into the directory where the FPGA Data Capture component is generated.
Launch the FPGA Data Capture App. This app is customized for your data capture signals.
Click the "Capture Data" button to start data capture. This requests one buffer of captured data from the FPGA. The default is to capture immediately, without waiting for a trigger condition.
The captured data is saved into a struct, dataCaptureOut, in the MATLAB workspace. If you have DSP System Toolbox, the captured data is also displayed as signal waveforms in the Logic Analyzer.
To capture data from the FPGA around a particular event, you can configure trigger conditions in the FPGA Data Capture App. For example, capture the audio data only after a counter reaches a certain value.
Select "counter" from the trigger signal dropdown, and click "+" button to enable this trigger signal. Then set the corresponding trigger condition to 10. The trigger mode would automatically change to "On trigger". This tells the FPGA to wait for the trigger condition before capturing and returning data. The GUI now looks like this:
Click Capture Data again. This time the data capture IP returns 1024 samples, captured when it detects the counter equals 10.
To capture a recurring event from the FPGA, configure Number of capture windows in the FPGA Data Capture App.
For example, to capture the audio data at eight different time slots, select the Number of capture windows to "8". The GUI should look like this:
Click Capture Data. The data capture IP returns eight windows of 128 samples each, which amounts to a total sample depth of 1024.
Window depth = Sample depth/Number of capture windows;
The result is seen in the Logic Analyzer as eight occurrences of the trigger, with the audio logged for 128 samples each:
Cursors added to differentiate the "Windows" and "Trigger position". Cursor with color Magenta is for trigger position and Cyan for end of each window.