Stream data from processor algorithms to shared memory
SoC Blockset / Processor I/O
The Stream Write block streams data from your processor algorithm to shared
memory in the Memory Channel block.
The Stream Write block has an internal counter that keeps track of the number
of empty buffers in the shared memory. After a successful read from memory, the memory sends a
done signal to the Stream Write block. Then, the block increments the counter,
asserting that a buffer is available in the memory. A write transaction is successful if at
least one buffer is available for writing. The Stream Write block sends a
True back to the software. You can use this status signal to
perform actions such as counting dropped frames or issuing rewrite requests.
In simulation, a timer-driven or event-driven task subsystem contains the Stream
Write block. The data signals from the software algorithm connect to the
Stream Write block. The write transaction is issued as a message to the
Memory channel block. After a read operation from shared memory, the
Memory Channel block notifies the Stream Write block of the
read event via the
data — Data frame from software algorithm
This port receives a data frame from the software algorithm. The block then streams the data as a message to a region of shared memory defined in the Memory Channel block.
status — Status of completed write transaction
This port sends a true status(
1) to the processor after a write
transaction to memory occurred. Use this status to count dropped frames.
Device name — Name of IP core device
ip:MM2S (default) | colon-separated list of IP core name and channel
The device name parameter is generated by the SoC Builder tool. Enter the name and channel of the IP core on the FPGA as a colon-separated list.
Enable event-based execution — Option to enable event-driven task execution
on (default) |
Select this parameter to use this block in event-driven task subsystems. In this case, the block writes to the Memory Channel block each time an empty buffer is available in the shared memory region.
Clear this parameter to use this block in timer-driven task subsystems. In this case, the block writes the data in the shared memory region at each sample time.
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
To automatically generate C code for your design, and execute on an SoC device, use the SoC Builder tool. To generate and execute C code for your SoC models, Embedded Coder® features are required. For more information on generating code for SoC designs, see Generate SoC Design.
The SoC Builder tool implements the Stream Write, Stream Read, Memory Channel, and Task Manager blocks with FPGA and processor IPs that use the AXI4-stream communication protocol. The AXI4-stream protocol uses a direct memory access (DMA) to read a data vector to a shared region on the external memory. This protocol enables high-speed streaming of data between the FPGA and the embedded processor through external memory.
Introduced in R2020b