Analyzing Models with Large Verification State Space
Persistent design variables (variables that are assigned in one time step and used in a later time step during simulation) affect the complexity of analysis in much the same way as input complexity. You can use one or more of the following techniques to simplify the complexity of the state space you want to search:
Apply constraints to input signals that are delayed.
Constrain the inputs to states that are contained within conditionally executed subsystems.
Limit the number of test case steps by setting the Maximum test case step parameter to
Increase the sample time for part or all of the model. (This procedure is similar to reducing timer thresholds, as described in Counters and Timers.) A test case that you generate at a lower sample rate often has similarities to the test case with a high sample rate that you need to achieve an objective.
Use tight variable types where ever possible. For example, if a flag with values of 0 or 1 only is defined as a
double, restrict the type to
States that are computed from previous state values present
a special challenge. For example, if you want to restrict the integrator
value in a PID controller, you can only use a set of values that includes
all reachable values from the initial
value. Otherwise, the input must be forced to
Neither of these limitations is practical and would probably make
the analysis less complete.
Alternatively, you can use existing simulation data to help satisfy your testing needs. If you have existing test data, run it on your model and collect model coverage. For an example of extending an existing test suite to achieve missing model coverage, see Extend an Existing Test Suite.