Variant Elements within Buses

Create Buses with Variant Conditions

This example shows how to create bus signals with elements having different variant conditions. This model has two signals (‘a’, ‘b’) that are merged to create a bus signal. These two signals have different variant conditions, V==1 and W == 1.

The bus selector is fed by two signals having two different variant conditions (V==1 and W==1). When this bus signal is fed into a bus selector and when you select the individual signals from the bus, the variant condition is also selected.

Note

Variant bus supports using Composite ports as input and output ports.

To see the completed model, open the slexVariantBus model.

Variant Condition Propagation with Bus

A Variant Source block can accept either virtual or nonvirtual bus inputs.

Consider this model.

Bus is created with variant conditions V = 1 and W = 1. When conditions V and W are propagated through the bus and when individual elements are selected from the bus, conditions are also selected.

Code Generation

You can generate code for the model. To do so, on the Apps tab of toolstrip, click Embedded Coder, then on the C Code tab, click Build. For more information on configuring model to generate code, see Prepare Variant-Containing Model for Code Generation.

When generating code with preprocessor conditionals, the bus types and hierarchies of all bus inputs must be the same.

Virtual and Nonvirtual Bus Behavior

Virtual buses provide the simplest approach for using buses to reduce signal clutter in a block diagram. Nonvirtual buses support modeling components (such as S-functions or MATLAB Function blocks) that require explicitly specified interfaces. There is no change in the propagation behavior of variant conditions when variant conditions are propagated through a virtual or nonvirtual bus.

Code generated for a virtual bus is as shown below.

/* Block states (default storage) for system '<Root>' */
typedef struct {

#if V == 1

real_T UnitDelay_1_DSTATE;           /* '<Root>/Unit Delay' */

#define D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS
#endif                                 /* V == 1 */
#if W == 1

int32_T UnitDelay_2_DSTATE;          /* '<Root>/Unit Delay' */
	
#define D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS
#endif                                 /* W == 1 */
	
#ifndef D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS
	
char _rt_unused;

#endif	
} D_Work_ex_bus_var_cond;

Code generated for a nonvirtual bus is as shown below.

/* Block states (default storage) for system '<Root>' */
typedef struct {
	
#if V == 1 || W == 1

myBus UnitDelay_DSTATE;              /* '<Root>/Unit Delay' */

#define D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS
#endif                                 /* V == 1 || W == 1 */

#ifndef D_WORK_EX_BUS_VAR_COND_VARIANT_EXISTS

char _rt_unused;

#endif
	
} D_Work_ex_bus_var_cond;
	

You must have an associated bus object in the bus, which provides properties that Simulink® uses to validate the bus signal. For more information on bus objects, see Specify Bus Properties with Bus Objects. The bus object used in the bus is unconditional and it generates unguarded code as shown below.

typedef struct {
real_T a;
int32_T b;
} myBus;

Variant Bus with Model Block

Consider this model containing a Model block.

This model has two signals (‘a’, ‘b’) which have different variant conditions, V==1 and V==2.

From the Model block, the bus selector is fed two signals having two different variant conditions (V==1 and V==2). When you select the individual signals from the bus, the variant conditions are also selected.

Known Limitations

  • Root bus element ports are not supported with variant elements.

  • Bus objects do not support variant elements.

  • State logging is not supported for a block (for example, Unit Delay) that takes in a bus in which some elements are removed.

Related Topics