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Results of Pre-Layout Analysis in Parallel Link

The Parallel Link Designer app produces one or more reports and logs for each simulation and process you run.

The tabs within a report are organized to aid in the process of progressive discovery. The first tab is the log tab, providing a progress summary of the analysis and its errors and warnings. The other tabs contain summaries of the data and successively more detailed information, letting you track down a particular result to a specific simulation file and transition number or time.

Validation Reports

Validation reports indicate the syntax errors in the data. When relevant, the reports provide the corresponding part name, IBIS file and component names, and timing file and model names.

ReportDescription
Validation SummaryNumber and location of warnings and errors.
Part Errors

Errors in the part properties file.

IBIS Errors

Syntax errors and omissions in the IBIS files. The report includes the signal name, model name, and number of the pin of the component in the IBIS file, and the IBIS model type for the model in the IBIS file.

Timing Errors

Syntax and consistency errors and omissions in the timing file data.

IBIS Timing Errors

Inconsistencies between IBIS components and timing models data. The report includes information about the pin of the component in the IBIS file, including the signal name, model name, timing model name, number, and I/O type. The report also includes the IBIS model type for the model in the IBIS file.

Coverage Warnings

Parts or pins in parts that are not referenced in the transfer netlist or timing model.

Transfer Net Summary

Details on each transfer net such as whether the type of the net is data, clock, or strobe, whether the net is differential or single-ended, and the number of nodes. This report also lists information on the clock, noise, and probe points.

Part Summary

Details on each part.

Model Overview

Lists every signal integrity, HSPICE, and IBIS parameter or extension associated with each model in the design. This includes model name, corner and mode information, waveform DRC and timing extensions among other parameters.

Part Pin Summary

Summary of part transfer nets and timing pin definitions.

Differential Pin Summary

Lists the differential pins and components associated with each part.

Timing Delay Summary

Summary of all output delays and setup and hold statements in each timing model.

Model Details

Lists most of the waveform DRC rules and timing levels used by the product. The report includes the actual parameter used (following the precedence rules) and the value assigned to that parameter.

Transfer Net Errors

Inconsistencies between transfer nets, IBIS components and timing models. The part, IBIS and timing files listed are not necessarily where the error occurred, but simply a listing of all files involved in the error checking.

Waveform and Timing Report

The waveform and timing report summarizes the waveform analysis and timing results for both pre-layout and post-layout simulations.

ReportDescription
Waveform Summary

Number of errors and warnings found during waveform analysis.

Waveform Fatal

Lists any fatal waveform error found on any edge during waveform processing. Fatal errors are errors that cause the inability to generate any waveform or timing data at all. This tab will only appear if there are fatal violations of the DRC rules.

Waveform Quality

Lists violations of waveform rules as applied to each edge. The product applies a number of waveform rules to each edge to verify that the transition meets various IC vendor AC specs including edge rate, ringback and monotonic (clock nets). If the transition violates any of these rules, the timing of the transition may be suspect.

Waveform Overshoot

Lists violations of these waveform overshoot rules. Overshoot does not affect the signaling operation of an I/O buffer but can affect the lifetime of an IC. Overshoot can occur in two ways: when the waveform instantaneously exceeds absolute overshoot limits set in the IBIS model, and when the waveform exceeds a lesser overshoot voltage limit for more than a prescribed time.

Eye Rollups

Lists a summary of eye details for each node in each transfer net.

Eye Details

Eye information for each receiver node in each simulation.

Derating Details

Details of slew-rate derating calculations. This tab will be present if one or more models contain slew rate derating tables.

Statistical

Variables and results from the statistical analysis simulation (STAT mode only).

Time Domain

Variables and results from the time domain analysis simulation (STAT mode only).

Xtalk Contours

Crosstalk and eye heights of the widebus sheets that have been simulated.

Waveform Margin by TNET

Summary of the waveform margins for each transfer net.

Waveform Margin by Variation

Summary of the waveform errors (if any) and waveform DRC margins associated with each simulation.

Model Overview

Summary of the data for each IBIS model used in the simulation. The report includes the measurement thresholds and the parameters that are used for each threshold.

Mask By Channel

Available when the analysis is defined using TiVW and ViVW (DDR4 and DDR5).

Mask By Receiver Corner

Available when the analysis is defined using TiVW and ViVW (DDR4 and DDR5).

Mask by Driver Receiver Corner

Available when the analysis is defined using TiVW and ViVW (DDR4 and DDR5).

Mask Training Details

Available in post-layout when the analysis is defined using TiVW and ViVW (DDR4 and DDR5).

Mask Eye Details

Available when the analysis is defined using TiVW and ViVW (DDR4 and DDR5).

Timing

Rolls up the By Variation Details tab by combining all transitions in the same transfer net.

By Transfers

Rolls up the By Variation tab by combining identical transfers (same driver and receiver).

By Variation

Includes setup margin, hold margin, etch delay, AC noise, transfer net, and extended net details.

By Variation DetailsContains the setup and hold margins for both rising and falling edges at each receiver in each simulation.
By Variation Details Summary

Available only in post-layout.

This tab contains two rows for each transfer net in the By Variation Details Summary Tab. One has the smallest setup margin for that transfer net, the other has the smallest hold margin for that transfer net.

By Driver

Rolls up the By Variation tab by combining identical drivers.

By Receiver

Rolls up the By Variation tab by combining identical receivers.

Synchronous Details

Contains the setup and hold margin for rising and falling data edges in each simulation.

Source Synchronous Details

Contains the setup and hold margin for rising and falling data edges in each simulation.

Dynamic Clock Skew

Lists the skews between the clock pins used in synchronous timing analysis.

Dynamic Clock Skew DetailsLists the source pins and calculations that are used to create the skews between the clock pins used in synchronous timing analysis.
No Strobe Details

Contains the details of source-synchronous constraints that do not have a strobe.

Coupling Pushout

Contains the coupling effects on timing.

Coupling Noise Tab

Contains the voltage variation on victim nets caused by coupling.

Edge Details

Summarizes each edge in each simulation.

Timing Waveform MarginRolls up timing margins, waveform DRC violations and waveform margins for each transfer net.
Model by Designator

Contains information about nets (transfer and extended), designator, parts, IBIS model, and timing model.

Model Details

Contains most of the waveform DRC rules and timing levels used by the product. The actual parameter used (following the precedence rules) and the value assigned to that parameter.

Assignment Report

Assignment reports contains the assignment summary report of transfer nets.

ReportDescription
Assign Netlist

Complete netlist with model data for each pin.

Swizzled Nets

List of nets whose connections appear to be incorrect. The tool looks at the logical pin names on all pins connected to a net and looks for inconsistencies that may indicate swapped bits of a bus. For example, if an extended net has a pin with logical name DATA0 on one device and a pin with logical name DATA7 on another device the net will be considered swizzled.

SPICE Generation Report

The SPICE generation report contains the SPICE generation log with information about the SPICE decks generated and any errors (HSPICE or IsSPICE). The report generates similar information for each of these processes:

  • Pre-layout simulation (single net)

  • Pre-layout simulation (all nets)

  • Post-layout simulation

To view the SPICE generation report after running a pre-layout or post-layout simulation, select Reports > SPICE Generation Report.

ReportDescription
Generate Spice Log

Number of simulation decks generated, errors in their generation and consistency checks.

Spice Decks

Data on the Spice decks generated listed by simulation name, including whether models are Spice or IBIS

Spice Deck Errors

List of reasons why a Spice deck was not generated.

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