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Parallel Link Design

Design parallel links such as DDR

The Parallel Link Designer app provides a dedicated system-level design and analysis environment for parallel links. Capture your parallel link designs graphically and experiment with different physical layouts and parameter sweeping to determine setup/hold timing and voltage margins for high-speed parallel links. Analyze parallel interfaces for compliance with timing and signal integrity constraints.

Use the Parallel Link Designer app to configure parallel links. Set simulation parameters, specify corner conditions, and define stimulus patterns. Set up pre-layout analysis to run SPICE and to conduct waveform and timing data analysis to analyze your custom parallel links. View and interpret the results using the Signal Integrity Viewer app. You can also set up and analyze the post-layout PCB database of your parallel link design if you have a license for RF PCB Toolbox™. You can modify the stackup and padstack models and customize vias and see how the changes impact your design.


Parallel Link DesignerAnalyze PCB designs for parallel link applications
Signal Integrity ViewerView the signal integrity results of Serial Link Designer or Parallel Link Designer app


SignalIntegrityProjectCreate Signal Integrity Toolbox project object
SignalIntegrityInterfaceReturn interface object of given Signal Integrity Toolbox project object
SignalIntegritySheetReturn sheet object of given Signal Integrity Toolbox interface object
SignalIntegrityStateReturn state object of given Signal Integrity Toolbox sheet object
SignalIntegritySimulationReturn simulation object of given Signal Integrity Toolbox sheet object
SignalIntegrityWaveformReturn waveform object of given Signal Integrity Toolbox simulation object


Parallel Link Design Basics

Configure Parallel Link Projects

Pre-Layout Analysis

Post-Layout Verification (Requires RF PCB Toolbox)

Results to View with Signal Integrity Viewer