Import and Verify Structured Text Code
Generate structured text code and test bench from your model. Verify the generated code by importing the generated code and test bench into your target IDE. You can verify that the output of the generated code matches the output of the model simulation by using the test bench data.
Generate, Import, and Verify Structured Text
This example shows how to import and verify your generated code by using the generated test bench:
Open the PLC Coder app. Click the PLC Code tab > Settings > PLC Code Generation.
Select the Generate testbench for subsystem check box. Click OK.
Click the PLC Code tab. Click Settings > Verify Code in IDE.
In the PLC Code tab, click Generate PLC Code.
When you select Verify Code in IDE, the software:
Generates the code and test bench.
Starts the target IDE.
Creates a project.
Imports the generated code and test bench to the new project in the target IDE.
Runs the generated code on the target IDE to verify it.
If you do not specify that the test bench code must be generated, when you verify
the generated code, you see the error
For information on:
IDEs not supported for automatic import and verification, see Troubleshoot Automatic Import Issues.
Possible reasons for long code generation time, see Troubleshooting: Long Test Bench Code Generation Time.
Troubleshooting: Long Test Bench Code Generation Time
When generating code that has a testbench and the test bench data size exceeds the limit that Simulink® PLC Coder™ can handle, it might result in long code generation times. The test bench data size depends on the number of times the input signal is sampled during simulation. When the simulation time is long or the simulation signals are sampled at a high frequency, the test bench data can be large.
To reduce test bench data size and code generation time, you can:
Reduce the duration of the simulation.
Increase the simulation step size.
If you want to retain the simulation duration and the step size, divide the simulation into multiple parts. For a simulation input signal that have the duration [0,
t], divide the input into multiple parts with durations [0,
t3], and so on, where
t1 < t2 < t3 < .. < t. Generate test bench code for each part separately and manually import them together to your IDE.