Design a PLL system starting from basic foundation blocks or from a family of reference architectures. Simulate and analyze the PLL system to verify key performance metrics until you meet the system specifications.
You can start by providing the specifications and impairments of each foundation block and connect the blocks to model different PLL architectural models (bottom-up approach). Alternatively, you can start from complete system-level models of typical PLL architectures and customize those models to meet your system specifications (top-down approach).
Use Measurements and Testbenches throughout the design process to verify the specifications of the blocks and of the entire system in presence of imperfections.
|Output a current proportional to the difference in duty cycle between two input ports (Since R2019a)
|Model second-, third-, or fourth-order passive loop filter (Since R2019a)
|Phase/frequency detector that compares phase and frequency between two signals (Since R2019a)
|Model voltage controlled oscillator (Since R2019a)
|Ring Oscillator VCO
|Model ring oscillator VCO (Since R2021a)
|Single Modulus Prescaler
|Integer clock divider that divides frequency of input signal (Since R2019a)
|Dual Modulus Prescaler
|Integer clock divider with two divider ratios (Since R2019a)
|Fractional Clock Divider with Accumulator
|Clock divider that divides frequency of input signal by fractional number (Since R2019a)
|Fractional Clock Divider with DSM
|Delta Sigma Modulator based fractional clock divider (Since R2019a)
|Fractional N PLL with Accumulator
|Frequency synthesizer with accumulator based fractional N PLL architecture (Since R2019a)
|Fractional N PLL with Delta Sigma Modulator
|Frequency synthesizer with delta sigma modulator based fractional N PLL architecture (Since R2019a)
|Integer N PLL with Dual Modulus Prescaler
|Frequency synthesizer with dual modulus prescaler based integer N PLL architecture (Since R2019a)
|Integer N PLL with Single Modulus Prescaler
|Frequency synthesizer with single modulus prescaler based integer N PLL architecture (Since R2019a)
- Phase Noise in Oscillators
Learn how to obtain reliable phase noise data from an oscillator data sheet.