HDL Filter Configuration Properties

Configure coefficients, complex input ports, and optional ports for specific filter types

With the HDL filter configuration properties, you can configure coefficients, complex input ports, and optional ports for specific filter types. For filter serialization and pipeline properties, see HDL Optimization Properties.

Specify these properties as comma-separated pairs of Name,Value arguments to the generatehdl function. Name is the property name and Value is the corresponding value. Name must appear inside single quotes (' '). You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

For example:

fir = dsp.FIRFilter('Structure','Direct form antisymmetric');
generatehdl(fir,'InputDataType',numerictype(1,16,15),'CoefficientSource','ProcessorInterface');

Coefficients

CoefficientSource — Source of programmable filter coefficients

'Internal' (default) | 'ProcessorInterface'

Source of programmable filter coefficients, specified as 'Internal' or 'ProcessorInterface'. This property applies only to Programmable Filter Coefficients for FIR Filters and Programmable Filter Coefficients for IIR Filters.

• 'Internal' — The coder obtains the filter coefficients from the filter object. The coefficients are hard-coded in the generated HDL code.

• 'ProcessorInterface' — The coder generates a memory interface for the filter coefficients. You can drive this interface with an external microprocessor. The generated VHDL entity or Verilog module for the filter includes these ports for the processor interface:

  • coeffs_in — Input port for coefficient data

  • write_address — Write-address for coefficient memory

  • write_enable — Write-enable signal for coefficient memory

  • write_done — Signal to indicate completion of coefficient write operation

  If you generate a test bench, you can specify the input stimulus for this interface by using the TestBenchCoeffStimulus property.

  For serial FIR filter, you can also specify the memory type for storing the programmable coefficients by setting the CoefficientMemory property.

CoefficientMemory — Memory type for programmable filter coefficients

'Registers' (default) | 'DualPortRAMs' | 'SinglePortRAMs'

Memory type for programmable filter coefficients, specified as 'Registers', 'DualPortRAMs', or 'SinglePortRAMs'. This property applies only to Programmable Filter Coefficients for FIR Filters with a fully serial, partly serial, or cascade serial architecture.

• 'Registers' — The coder generates a register file for storing programmable coefficients.

• 'SinglePortRAMs' or 'DualPortRAMs' — The coder generates the respective RAM interface for storing programmable coefficients.

Dependencies

This property applies only when you set CoefficientSource to 'ProcessorInterface'. If the coder does not generate an interface for programmable coefficients, this CoefficientMemory property is ignored.

Optional Ports

InputComplex — Generate complex input data ports

'off' (default) | 'on'

Generate complex input data ports, specified as 'off' or 'on'. Use this option when your filter design requires complex input data. See Using Complex Data and Coefficients. When you set this property to 'on', the coder generates ports and signal paths for the real and imaginary components of a complex signal.

You can customize the port names by setting the ComplexRealPostfix and ComplexImagPostfix properties.

Dependencies

To generate complex inputs, you must also set CoefficientSource to 'Internal'. Complex inputs are not supported when filter coefficients are obtained from a processor interface.

ClockInputs — Type of generated clock inputs

'Single' (default) | 'Multiple'

Type of generated clock inputs, specified as 'Single' or 'Multiple'. This property applies only to Multirate Filters.

• 'Single' — The generated VHDL entity or Verilog module for the filter has a single clock input, an associated clock enable input, and a clock enable output. The generated code includes a counter that controls the timing of data transfers to the filter output (for decimation filters) or input (for interpolation filters). The counter behaves as a secondary clock. The decimation or interpolation factor determines the clock rate of the counter. This option provides a self-contained clocking solution for FPGA designs.

  To customize the names of these clock inputs and outputs, see the ClockInputPort, ClockEnableInputPort, and ClockEnableOutputPort properties.

  Interpolators also pass through the clock enable input signal to an output port named ce_in. This signal indicates when the object accepted an input sample. You can use this signal to control the upstream data flow. You cannot customize this port name.

• 'Multiple' — The generated VHDL entity or Verilog module for the filter has separate clock inputs for each rate of the multirate filter. Each clock input has an associated clock enable input. The coder does not generate a clock enable output. Provide input clock signals that correspond to the desired decimation or interpolation factor.

  This option provides more flexibility than a single clock input. However, multiple clock inputs assume that you provide higher-level HDL code to drive the input clocks of your filter. The coder does not generate synchronizers between multiple clock domains. If you generate a test bench, examine the clk_gen processes for each clock.

  The following filters do not support 'Multiple':

  • Filters with a partly serial architecture

  • Multistage sample rate converters: dsp.FIRRateConverter, dsp.FarrowRateConverter, or multirate dsp.FilterCascade

For an example, see Clock Ports for Multirate Filters.

AddRatePort — Generate rate ports

'off' (default) | 'on'

Generate rate ports, specified as 'off' or 'on'. This property applies only to Variable Rate CIC Filters.

When you set this property to 'on', the coder generates rate and load_rate ports for the filter. A variable-rate CIC filter has a programmable rate change factor. When you assert the load_rate signal, the rate port loads in a rate factor. You can generate rate ports only for a full-precision filter.

If you generate a test bench, you can customize the rate port stimulus by setting the TestBenchRateStimulus property.

FracDelayPort — Name of fractional delay input port

'filter_fd' (default) | character vector | string scalar

Name of fractional delay input port, specified as 'filter_fd', a character vector, or a string scalar. This property applies only to Single-Rate Farrow Filters. For example:

farrowfilt = dsp.VariableFractionalDelay('InterpolationMethod','Farrow');
generatehdl(farrowfilt,'InputDataType',numerictype(1,18,17), ...
    'FractionalDelayDataType',numerictype(1,8,7), ...
    'FracDelayPort','fractional_delay');

If you specify a value that is a reserved word in the target language, the coder adds the postfix _rsvd to this value. You can update the postfix value by using the ReservedWordPostfix property. For more details, see Resolving HDL Reserved Word Conflicts.

If you generate a test bench, you can customize the fractional delay stimulus by setting the TestBenchFracDelayStimulus property.

Tips

If you use the fdhdltool function to generate HDL code, you can set the corresponding properties in the Generate HDL dialog box.

Filter Type	Property	Location in Dialog Box
FIR or IIR filter with programmable coefficients	Coefficient source	Filter Architecture tab
FIR filter with serial architecture and programmable coefficients	Coefficient memory	Filter Architecture tab, when Coefficient source is set to Processor interface
Filter with complex input data	Input complexity	Global Settings tab > Ports tab
Multirate filter	Clock inputs	Global Settings tab
CIC filter	Add rate port	Filter Architecture tab
Single-rate Farrow filter	Fractional delay port	Global Settings tab > Ports tab