Microchip FPGA and SoC Devices
R2026bHDL Coder™ Support Package for Microchip FPGA and SoC Devices enables you to generate HDL IP cores from MATLAB® and Simulink® designs and integrate them into Altera® FPGA designs using Microchip Libero® SoC. You can generate synthesizable HDL code, package it as an IP core, integrate it into your Libero project, and program Microchip devices.
The support package includes board definition files for supported Microchip FPGA and SoC boards and supports FPGA‑in‑the‑Loop (FIL) simulation, which enables you to verify HDL designs by running them on development boards using MATLAB or Simulink testbenches.
This support package includes reference designs for popular Microchip development kits, so you can generate HDL code and port mappings to I/O, AXI registers, and DDR memory interfaces. It additionally supports the HDL Coder custom reference design API to develop reference designs for a variety of development boards based on Microchip devices.
To deploy your design to the Microchip FPGA or SoC device, you must install the HDL Coder Support Package for Microchip FPGA and SoC Devices. For installation information, see HDL Coder Supported Hardware.
Categories
- Setup and Configuration
Download and install support package for use with third-party EDA tools and supported hardware
- Custom IP Core Generation
Generate HDL IP core from your DUT for deployment to the default system reference design or custom reference design registered with the board
- Custom Board and Reference Design
Define and register custom reference design or custom board for Microchip SoC device
- Deployment
Create bitstream containing user programming and download it to Microchip SoC platform
- FPGA-in-the-Loop Simulation
Verification with FPGA hardware



