Digital Signal Processing
R2026bDevelop signal processing algorithm by using MATLAB® functions or Simulink® blocks. You can use the blocks from DSP HDL Toolbox and DSP System Toolbox that are supported for HDL code generation. DSP HDL Toolbox provides blocks and system objects that implement hardware-friendly architectures and support HDL code generation when used with HDL Coder™. The DSP HDL Toolbox blocks and system objects also have high-throughput streaming interfaces that achieve gigasamples-per-second (GSPS), also called super sample rates, hardware control signals, and options to select different hardware implementations of their algorithms. The DSP System Toolbox product provides algorithms, apps, and scopes for designing, simulating, and analyzing signal processing systems.
For filtered lists of DSP HDL Toolbox and DSP System Toolbox blocks supported for HDL code generation, see DSP HDL Toolbox Block List (HDL Code Generation) (DSP HDL Toolbox) and DSP System Toolbox Block List (HDL Code Generation) (DSP System Toolbox), respectively.
Topics
MATLAB Algorithms
- Generate HDL and HLS Code from an LMS Filter Algorithm
This example shows how to generate HDL and HLS code from a MATLAB® design that implements an LMS (Least Mean Squares) adaptive filter. - Generate HDL and HLS Code from a Bisection Square Root Algorithm
This example shows how to generate HDL and HLS code from a MATLAB design that computes the square root of an unsigned fixed-point number using the bisection algorithm.
Simulink Algorithms
- High-Throughput Channelizer for FPGA (DSP HDL Toolbox)
Implement a polyphase filter bank channelizer with throughput of gigasamples-per-second (GSPS). (Since R2022a) - Implement Digital Downconverter for FPGA (DSP HDL Toolbox)
Design a digital downconverter (DDC) for LTE on FPGAs. - Implement Digital Upconverter for FPGA (DSP HDL Toolbox)
Design a digital upconverter (DUC) for LTE on FPGAs.
Related Information
Featured Examples
Programmable FIR Filter for FPGA
Implement a programmable FIR filter for hardware and load the filter coefficients by using a memory-style interface.
Multichannel FIR Filter for FPGA
Implement a discrete FIR filter with multiple input data streams for hardware and then increase the area efficiency of the filter on hardware.
FPGA-Based Monopulse Technique: Algorithm Design
Develop a monopulse technique to perform digital downconversion on hardware (Part 1).
Rectangular Array MVDR Beamformer
Implement a minimum-variance distortionless-response (MVDR) beamformer for a 4x4 rectangular antenna array on FPGA.
Implement an Audio Filter on an Intel Board
In this example, we illustrate how to:
Implement an Audio Filter on a Zynq Board
Model an audio system and implement it on a Zynq® board using an audio reference design.
