Code Generation from Simulink Models
R2026bImplement your Simulink model or subsystem in hardware by generating HDL code and deploying that code on an Application-Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA). Design the model with blocks that are compatible with HDL code generation. If the model uses floating-point data, use Fixed-Point Designer™ to convert it to a fixed-point model. Apply optimizations to generate more hardware-efficient HDL code. After you generate HDL code and verify that it matches your original algorithm, deploy the HDL code on your target hardware.
Functions
Topics
Simulink to HDL Code Generation
- Set HDL Code Generation Options
Access HDL options in the Configuration Parameters dialog box, Simulink toolstrip, block context menu, or HDL Block Properties window. - Generate HDL Code from Simulink Model Using Configuration Parameters
Use the Configuration Parameters dialog box to generate HDL code for your Simulink model. - Generate HDL Code from Simulink Model from Command Line
Use the command-line function makehdl to generate HDL code for your Simulink model. - HDL Code Generation and FPGA Synthesis from Simulink Model
Generate code and synthesize your Simulink design on the target FPGA.
Basic Code Generation Practices
- Generate DUT Ports for Tunable Parameters
Generate tunable parameters as top-level DUT ports. - Obfuscate Generated HDL Code from Simulink Models
Learn how to obfuscate the generated VHDL®, Verilog® or SystemVerilog code from your model. - Scalarization of Vector Ports in Generated VHDL Code
Flatten vector signals on entire model or at DUT level into a structure of scalar signals in generated VHDL or SystemVerilog code. - Add Comments to Generated HDL Code
Add comments to generated HDL code by using Simulink annotations, signal descriptions, DocBlock blocks, or requirement links. - Use Test Points to Debug Signals with HDL Coder
An example that shows how to add test points to signals in your model and debug these signals in the generated HDL code. - Generation of Clock Bundle Signals in HDL Coder
How HDL Coder™ generates clock, reset, and clock enable signals in the HDL code.
Featured Examples
Simulate and Generate HDL Code for the Float Typecast Block
Use the Float Typecast block to cast an input signal to floating-point or fixed-point.
Generate SystemVerilog Code for a Simulink Model
Generate SystemVerilog HDL code from a Simulink® model. SystemVerilog code has more advanced features over that Verilog® code, such as the use of array ports, package declarations, structure ports and more.
Convert Input Vector of Bits to Integer
Use the Bits to Word block in a Simulink® Model that converts vector of bits to an unsigned integer. You also generate HDL code for the model.
Convert Integer to Vector of Bits
Implement the Word to Bits block in a Simulink® Model that converts an integer to a vector of bits. You also generate HDL code for the model.
Implement Sqrt Block with Control Signals
Implement the control-signal based Square root block and use it to generate HDL code.
Implement rSqrt Block with Control Signals
Implement the control-signal based reciprocal square root block and use it to generate HDL code.
Implement Divide Block with Control Signals
Implement the control-signal based Divide block and use it to generate HDL code.
Implement Reciprocal Block with Control Signals
Implement the control-signal based Reciprocal block and use it to generate HDL code.
Implement Atan2 Block with Control Signals
Implement the control-signal based Atan2 block and use it to generate HDL code.
Implement Sine and Cosine Block with Control Signals
Implement the control-signal based SinCos block and use it to generate HDL code.
