Modulo by Constant HDL Optimized

R2026b

Perform mod operation with a constant denominator and generate optimized HDL code

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Modulo by Constant HDL Optimized block

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Libraries:
Fixed-Point Designer HDL Support / Math Operations

Description

The Modulo by Constant HDL Optimized block performs the modulo operation (remainder after division) with a constant denominator using an HDL-optimized architecture with cycle-true latency.

The Modulo by Constant block uses an algorithm that is functionally similar to a Barrett Reduction. The division operation is computed via a multiplication by inverse, which generally results in better performance on embedded systems.

Examples

Implement HDL Optimized Modulo by Constant

How to use the Modulo by Constant HDL Optimized block.

• Open Script

Ports

Input

X — Dividend

real-valued scalar | vector | matrix | multidimensional array

Dividend, specified as a real-valued scalar, vector, matrix, or multidimensional array.

If X is a fixed-point data type, it must use binary-point scaling. Slope-bias representation is not supported for fixed-point data types.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | fixed point

validIn — Whether input is valid

boolean scalar

Whether input is valid, specified as a Boolean scalar. This control signal indicates when the data from the X input port is valid. When this value is 1 (true), the block captures the value on the X input port. When this value is 0 (false), the block ignores the input samples.

Data Types: Boolean

Output

Y — Result of modulus operation

scalar | vector | matrix | multidimensional array

Result of modulus operation, returned as a scalar, vector, matrix, or multidimensional array.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | fixed point

validOut — Whether output data is valid

boolean scalar

Whether the output data is valid, returned as a Boolean scalar. When the value of this control signal is 1 (true), the block has successfully computed the output Y. When this value is 0 (false), the output data is not valid.

Data Types: Boolean

Parameters

Denominator — Divisor

10 (default) | real-valued scalar | vector | matrix | multidimensional array

Divisor to use for the modulus operation, specified as a positive, real-valued, finite scalar, vector, matrix, or multidimensional array.

Programmatic Use

Block Parameter: Denominator

Type: character vector

Values: MATLAB® expression that evaluates to a positive, real-valued, finite fixed point or numeric value

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

Default: '10'

Programmatic Use: Add Block

To add the block programmatically, use the add_block function with one of these library block paths as the source.

"embeddedMatrixLib/Math Operations/Modulo by Constant HDL Optimized"

Example: add_block("embeddedMatrixLib/Math Operations/Modulo by Constant HDL Optimized","myModel/myBlock",MakeNameUnique="on")

Algorithms

Modulo Operation

The modulo operation,

$$Y=X\mathrm{mod}D=X-\lfloor \frac{X}{D}\rfloor \times D$$

is an important building block for many mathematical algorithms. However, this formula for X mod D is computationally inefficient for fixed-point and integer inputs. Many embedded processors lack instructions for integer division. Those that do have them require many clock cycles to compute the answer. Division is also inefficient in commercially-available FPGAs, whose arithmetic circuits are designed for efficient multiplication, addition, and subtraction. Finally, for fixed-point modulo operations, it is difficult to optimize the word length of internal data types used for the calculation because the division operation is unbounded, even for small-wordlength inputs.

The denominator in the modulo problem is a compile-time constant, so the block can compute the floored division by using a multiplication followed by a cast. Rewriting the division operation as

$$\frac{X}{D}=X\times \frac{1}{D}$$

shows this. The constant is calculated to the precision necessary to maintain both accuracy and computational efficiency. The cast that follows discards any fractional bits, which is an efficient operation on both microprocessors and FPGAs.

The Modulo by Constant block uses an algorithm that is functionally similar to a Barrett Reduction. The division operation is computed via a multiplication by inverse, which generally results in better performance on embedded systems.

Latency

The Modulo by Constant HDL Optimized block performs the modulo operation (remainder after division) with a constant denominator using an HDL-optimized architecture with cycle-true latency.

The latency is:

• 0 when Denominator is a power of 2

• 4 otherwise

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Slope-bias representation is not supported for fixed-point data types.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays in the design. Distributed pipelining does not redistribute these registers. The default value is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

Slope-bias representation is not supported for fixed-point data types.

Version History

Introduced in R2021a

R2024a: Latency of Modulo by Constant HDL Optimized block reduced

The latency of the Modulo by Constant HDL Optimized block has been reduced from 9 clock cycles to 4 clock cycles.

R2023b: Support for vector and matrix input

The Modulo by Constant HDL Optimized block now supports vector and matrix inputs.

R2023b: Modulo by Consant block supported for use in For Each Subsystem block

The Modulo by Constant HDL Optimized block is supported for use inside a For Each Subsystem block.