Complex Burst Matrix Solve Using Qless QR Decomposition
Compute the value of X in the equation A'AX = B for complexvalued matrices using Qless QR decomposition
Since R2020a
Libraries:
FixedPoint Designer HDL Support /
Matrices and Linear Algebra /
Linear System Solvers
Description
The Complex Burst Matrix Solve Using Qless QR Decomposition block solves the system of linear equations, A'AX = B, using Qless QR decomposition, where A and B are complexvalued matrices.
When Regularization parameter is nonzero, the Complex Burst Matrix Solve Using Qless QR Decomposition block solves the matrix equation
$${\left[\begin{array}{c}\lambda {I}_{n}\\ A\end{array}\right]}^{\text{'}}\cdot \left[\begin{array}{c}\lambda {I}_{n}\\ A\end{array}\right]X=\left({\lambda}^{2}{I}_{n}+A\text{'}A\right)X=B$$
where λ is the regularization parameter,
A is an mbyn matrix, and
I_{n} =
eye(n)
.
Examples
Ports
Input
A(i,:) — Rows of matrix A
vector
Rows of matrix A, specified as a vector. A is an mbyn matrix where m ≥ 2 and m ≥ n. If B is single or double, A must be the same data type as B. If A is a fixedpoint data type, A must be signed, use binarypoint scaling, and have the same word length as B. Slopebias representation is not supported for fixedpoint data types.
Data Types: single
 double
 fixed point
Complex Number Support: Yes
B(i,:) — Rows of matrix B
vector
Rows of matrix B, specified as a vector. B is an nbyp matrix where n ≥ 2. If A is single or double, B must be the same data type as A. If B is a fixedpoint data type, B must be signed, use binarypoint scaling, and have the same word length as A. Slopebias representation is not supported for fixedpoint data types.
Data Types: single
 double
 fixed point
validIn — Whether inputs are valid
Boolean
scalar
Whether inputs are valid, specified as a Boolean scalar. This control signal
indicates when the data from the A(i,:)
and
B(i,:)
input ports are valid. When this value is
1
(true
) and the ready
value is 1
(true
), the block captures the values
at the A(i,:)
and B(i,:)
input ports. When
this value is 0
(false
), the block ignores the
input samples.
After sending a true
validIn
signal, there may be some delay before
ready
is set to false
. To ensure all data is
processed, you must wait until ready
is set to
false
before sending another true
validIn
signal.
Data Types: Boolean
restart — Whether to clear internal states
Boolean
scalar
Whether to clear internal states, specified as a Boolean scalar. When this value
is 1 (true
), the block stops the current calculation and clears all
internal states. When this value is 0 (false
) and the
validIn
value is 1 (true
), the block begins
a new subframe.
Data Types: Boolean
Output
X(i,:) — Rows of matrix X
scalar  vector
Rows of the matrix X, returned as a scalar or vector.
Data Types: single
 double
 fixed point
validOut — Whether output data is valid
Boolean
scalar
Whether the output data is valid, returned as a Boolean scalar. This control
signal indicates when the data at the output port X(i,:)
is valid.
When this value is 1
(true
), the block has
successfully computed a row of X. When this value is
0
(false
), the output data is not
valid.
Data Types: Boolean
ready — Whether block is ready
Boolean
scalar
Whether the block is ready, returned as a Boolean scalar. This control signal
indicates when the block is ready for new input data. When this value is
1
(true
) and the validIn
value is 1
(true
), the block accepts input data
in the next time step. When this value is 0
(false
), the block ignores input data in the next time
step.
After sending a true
validIn
signal, there may be some delay before
ready
is set to false
. To ensure all data is
processed, you must wait until ready
is set to
false
before sending another true
validIn
signal.
Data Types: Boolean
Parameters
Number of rows in matrix A — Number of rows in matrix A
4
(default)  positive integervalued scalar
Number of rows in matrix A, specified as a positive integervalued scalar.
Programmatic Use
Block Parameter:
m 
Type: character vector 
Values: positive integervalued scalar 
Default:
4 
Number of columns in matrix A and rows in matrix B — Number of columns in matrix A and rows in matrix B
4
(default)  positive integervalued scalar
Number of columns in matrix A and rows in matrix B, specified as a positive integervalued scalar.
Programmatic Use
Block Parameter:
n 
Type: character vector 
Values: positive integervalued scalar 
Default:
4 
Number of columns in matrix B — Number of columns in matrix B
1
(default)  positive integervalued scalar
Number of columns in matrix B, specified as a positive integervalued scalar.
Programmatic Use
Block Parameter:
p 
Type: character vector 
Values: positive integervalued scalar 
Default:
1 
Regularization parameter — Regularization parameter
0 (default)  real nonnegative scalar
Regularization parameter, specified as a nonnegative scalar. Small, positive values of the regularization parameter can improve the conditioning of the problem and reduce the variance of the estimates. While biased, the reduced variance of the estimate often results in a smaller mean squared error when compared to leastsquares estimates.
Programmatic Use
Block Parameter:
regularizationParameter 
Type: character vector 
Values: real nonnegative scalar 
Default:
0 
Output datatype — Data type of output matrix X
fixdt(1,18,14)
(default)  double
 single
 fixdt(1,16,0)
 <data type expression>
Data type of the output matrix X, specified as
fixdt(1,18,14)
, double
,
single
, fixdt(1,16,0)
, or as a userspecified
data type expression. The type can be specified directly, or expressed as a data type
object such as Simulink.NumericType
.
Programmatic Use
Block Parameter:
OutputType 
Type: character vector 
Values:
'fixdt(1,18,14)'  'double' 
'single'  'fixdt(1,16,0)' 
'<data type expression>' 
Default:
'fixdt(1,18,14)' 
Tips
Use fixed.getQlessQRMatrixSolveModel(A,B)
to generate a template model
containing a Complex Burst Matrix Solve Using Qless QR Decomposition block for
complexvalued input matrices A
and B
.
Algorithms
Choosing the Implementation Method
Systolic implementations prioritize speed of computations over space constraints, while burst implementations prioritize space constraints at the expense of speed of the operations. The following table illustrates the tradeoffs between the implementations available for matrix decompositions and solving systems of linear equations.
Implementation  Throughput  Latency  Area 

Systolic  C  O(n)  O(mn^{2}) 
PartialSystolic  C  O(m)  O(n^{2}) 
PartialSystolic with Forgetting Factor  C  O(n)  O(n^{2}) 
Burst  O(n)  O(mn)  O(n) 
Where C is a constant proportional to the word length of the data, m is the number of rows in matrix A, and n is the number of columns in matrix A.
For additional considerations in selecting a block for your application, see Choose a Block for HDLOptimized FixedPoint Matrix Operations.
Synchronous vs Asynchronous Implementation
The Matrix Solve Using QR Decomposition blocks operate synchronously. These blocks first decompose the input A and B matrices into R and C matrices using a QR decomposition block. Then, a back substitute block computes RX = C. The input A and B matrices propagate through the system in parallel, in a synchronized way.
The Matrix Solve Using Qless QR Decomposition blocks operate asynchronously. First, Qless QR decomposition is performed on the input A matrix and the resulting R matrix is put into a buffer. Then, a forward backward substitution block uses the input B matrix and the buffered R matrix to compute R'RX = B. Because the R and B matrices are stored separately in buffers, the upstream Qless QR decomposition block and the downstream Forward Backward Substitute block can run independently. The Forward Backward Substitute block starts processing when the first R and B matrices are available. Then it runs continuously using the latest buffered R and B matrices, regardless of the status of the Qless QR Decomposition block. For example, if the upstream block stops providing A and B matrices, the Forward Backward Substitute block continues to generate the same output using the last pair of R and B matrices.
The Burst (Asynchronous) Matrix Solve Using Qless QR Decomposition blocks are available in both synchronous and asynchronous operation variants, as denoted by the block name.
AMBA AXI Handshake Process
This block uses the AMBA AXI handshake protocol [1]. The valid/ready
handshake process is used to transfer data and control information. This twoway control mechanism allows both the manager and subordinate to control the rate at which information moves between manager and subordinate. A valid
signal indicates when data is available. The ready
signal indicates that the block can accept the data. Transfer of data occurs only when both the valid
and ready
signals are high.
Block Timing
The Burst Matrix Solve Using Qless QR Decomposition blocks accept and process A and B matrices row by row synchronously. After accepting m rows, the block outputs the X matrix row by row continuously. The matrix is output from the first row to the last row.
For example, assume that the input A and B
matrices are 3by3. Additionally assume that validIn
asserts before
ready
, meaning that the upstream data source is faster than the QR
decomposition.
In the figure,
A1r1
is the first row of the first A matrix,X1r3
is the third row of the first X matrix, and so on.validIn
toready
— From a successful row input to the block being ready to accept the next row within one matrix.Last row
validIn
tovalidOut
— From the last row input to the block starting to output the solution.Last row
validIn
to new matrix ready — From the block starting to output the solution to the block ready to accept the next matrix input.
The following table provides details of the timing for the Complex Burst Matrix Solve Using Qless QR Decomposition block. Latency depends on the size of matrix A and the data types of the A and B matrices. In the table:
In the table, m represents the number of rows in matrix A, and n is the number of columns in matrix A. wl represents the word length of the input data.
m is the number of rows in matrix A.
n is the number of columns in matrix A.
wl represents the word length of the input data in matrix A.
Input Data Type  validIn to ready (cycles)  Last Row validIn to validOut
(cycles)  Last row validIn to new matrix ready (cycles) 

Fixed point fi  (wl*2 + 11)*n + 2  7*n^{2} + 33*n + 6 + 4*n*wl + 2*n*nextpow2(wl)  7*n^{2} + 33*n + 6 + 4*n*wl + 2*n*nextpow2(wl) + n 
Scaled double fi  (wl*2 + 11)*n + 2  7*n^{2} + (4*wl + 31)*n + 6  7*n^{2} + (4*wl + 31)*n + 6 + n 
double  117*n + 2  7*n^{2} + 135*n + 6  7*n^{2} + 135*n + 6 + n 
single  59*n + 2  7*n^{2} + 77*n + 6  7*n^{2} + 77*n + 6 + n 
Hardware Resource Utilization
This block supports HDL code generation using the Simulink^{®} HDL Workflow Advisor. For an example, see HDL Code Generation and FPGA Synthesis from Simulink Model (HDL Coder) and Implement Digital Downconverter for FPGA (DSP HDL Toolbox).
This example data was generated by synthesizing the block on a Xilinx^{®} Zynq^{®} UltraScale™ + RFSoC ZCU111 evaluation board. The synthesis tool was Vivado^{®} v.2020.2 (win64).
The following parameters were used for synthesis.
Block parameters:
m = 16
n = 16
p = 1
Matrix A dimension: 16by16
Matrix B dimension: 16by1
Input data type:
sfix16_En14
Target frequency: 250 MHz
The following tables show the post placeandroute resource utilization results and timing summary, respectively.
Resource  Usage  Available  Utilization (%) 

CLB LUTs  30915  425280  7.27 
CLB Registers  34833  850560  4.10 
DSPs  12  4272  0.28 
Block RAM Tile  0  1080  0.00 
URAM  0  80  0.00 
Value  

Requirement  4 ns 
Data Path Delay  3.686 ns 
Slack  0.296 ns 
Clock Frequency  269.98 MHz 
References
[1] "AMBA AXI and ACE Protocol Specification Version E." https://developer.arm.com/documentation/ihi0022/e/AMBAAXI3andAXI4ProtocolSpecification/SingleInterfaceRequirements/Basicreadandwritetransactions/Handshakeprocess
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
Slopebias representation is not supported for fixedpoint data types.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has one default HDL architecture.
General  

ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

Supports fixedpoint data types only.
Version History
Introduced in R2020aR2022a: Support for Tikhonov regularization parameter
The Complex Burst Matrix Solve Using Qless QR Decomposition block now supports the Tikhonov Regularization parameter.
R2021a: Reduced HDL resource utilization
This block now has an improved algorithm to reduce resource utilization on hardwareconstrained target platforms.
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