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why exportONNXNetwork will add additional "Sub" in onnx, how to remove this layer in onnx?
Hi, i did the following: >> baseNetwork = resnet50; >> exportONNXNetwork(baseNetwork,'resnet50-matlab'); but when compare sam...
mehr als 6 Jahre vor | 1 Antwort | 0
1
AntwortFrage
how to deploy deep learning prototype to FPGA using HDL Coder?
Hi i have FPGA platform and like to play around with Matlab deep learning (like MatConvNet), then deploy on my FPGA platform fo...
etwa 8 Jahre vor | 1 Antwort | 0
1
AntwortFrage
running open_system('hdlcoder_led_blinking') for zynq, but no connection?
Hi, i am using usb jtag cable for communication with zynq-zc702, but i can't see serialport as instructed in the webinar, how sh...
etwa 12 Jahre vor | 1 Antwort | 0
1
AntwortFrage
how could i generate an axi-stream or axi4-lite dma master by hdl coder?
Hi, i found the current demo using only axi-stream slave interface in sobel image processing system. however, it might require a...
etwa 12 Jahre vor | 1 Antwort | 0
1
AntwortFrage
HDL Stream FFT in HDL Coder 2013b, not support AXI4-Stream Interface? (single rate?)
Hi, i have built a system involving Stream FFT with AXI4-Stream Interface, the goal is to put this design into Zynq, so AXI4-St...
etwa 12 Jahre vor | 1 Antwort | 0
1
AntwortFrage
Failed Streaming interface is not supported when the DUT is not single rate
Hi, the AXI-Stream interface for Stream FFT is requiring DUT "single rate", but i can't find where to set it, and what does it ...
etwa 12 Jahre vor | 0 Antworten | 0
0
AntwortenFrage
HDL Stream FFT in HDL Coder 2013b, not support FPGA?
Hi, i am using Stream FFT for Zynq, but once i have created the subsystem and set it to Atomic, i have this error message pop u...
etwa 12 Jahre vor | 1 Antwort | 0
1
AntwortFrage
How to create a FFT ipcore for Zynq using Simulink HDL Coder?
there is an error message "not support for frame based module"? is there any other solution for exporting signal processing bl...
mehr als 12 Jahre vor | 2 Antworten | 1
2
AntwortenFrage
Does HDL coder from Simulink support AXI-4 Stream Interface for Xilinx Zynq?
Hi all, I have created an adder example and export to Xilinx Vivado 2013.2 using HDL coder, and integrated using Vivado IPI. th...
mehr als 12 Jahre vor | 1 Antwort | 0
