I am trying to use the Matlab Simulink HDL Coder with the help of a custom toolbox that generates Matlab function blocks. Inside of the function code, there is an addition of two numbers, one represented by a 16-bit integer quantity, such as: "if ((a + 50) > b)", where a and b are going to be represented by 16-bit integers. When I generate Verilog HDL code for an Altera FPGA after ensuring that the model is compatible with the Compatibility Check, the code it generates has the form as seen below:
module code
(
a,
b,
output_rsvd
);
input signed [15:0] a; // int16
input signed [15:0] b; // int16
output output_rsvd;
reg output_rsvd_1;
reg signed [16:0] add_temp_1; // sfix17
reg signed [15:0] cast_1; // int16
reg signed [16:0] add_temp_0_1; // sfix17
reg signed [15:0] cast_0_1; // int16
always @(a, b) begin
//
output_rsvd_1 = 1'b1;
add_temp_1 = a + 50;
if ((add_temp_1[16] == 1'b0) && (add_temp_1[15] != 1'b0)) begin
cast_1 = 32767;
end
else if ((add_temp_1[16] == 1'b1) && (add_temp_1[15] != 1'b1)) begin
cast_1 = -32768;
end
else begin
cast_1 = add_temp_1[15:0];
end
if (cast_1 > b) begin
output_rsvd_1 = 1'b1;
end
else begin
//...
assign output_rsvd = output_rsvd_1;
endmodule // code
It is obviously checking for overflow/underflow from the 16 bit integer to a 17 bit integer which is possible with the addition of 50, however, with the current design of our project, the overflow case will never happen as a will never get that big, and therefore we would like to remove the over-/underflow check, as it is causing the HDL code to generate odd behaviour that is causing additional issues, and additionally, it would waste a large amount of space on the FPGA assuming it did work. We have tried limiting the inputs on the ports to numbers that would never cause an over-/underflow, but this did not fix the issue. Is there any way to disable the auto-generated over-/underflow checking created by Simulink HDL Coder in this manner?
