HDL simulinks coder error

11 Ansichten (letzte 30 Tage)
Pham Van Dung
Pham Van Dung am 18 Apr. 2012
Dear Tim McBrayer,
When I tried to convert my Simulink file to VHDL code and I used HDL Workflow Advisor, but in step 3.2: Generate RTL Code and Testbench , i have an error:
Error due to multiple causes.
Failed Generated HDL code.
Don't have any informations for me to solve this problems
Please help me!
Thankyou very much!
Best Regard.

Melden Sie sich an, um diese Frage zu beantworten.

Akzeptierte Antwort

Tim McBrayer
Tim McBrayer am 23 Apr. 2012
There's no information to respond to here. Sorry, but there's nothing useful I can add.

Weitere Antworten (0)

Kategorien

Mehr zu AMD FPGA and SoC Devices finden Sie in Help Center und File Exchange

Tags

Produkte

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by