Tool boxes required to generate IP CORE from SIMULINK
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Hello,
I saw an video (Create simple "Add" Block, and generate RTL by HDL Coder in Simulink [HDL coder + Zynq Project]) which clearly shows that we can generate IP CORE from Simulink. Apart from the products MATLAB and Simulink, what are the other toolboxes that are required to generate an IP CORE using this workflow (to port on Zynq FPGA)?
Thanks
Pankaja
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