data synchronization between two control blocks in simulink

I have modelled control algorithm in simulink that takes inputs from ADC. The total design is divided into two blocks, one is ADC block that sends trigger signals to ADC and acquires the data. The other is the control block. The sampling time for control block is 20KHz . I propose to implement these blocks in FPGA with one external clock of 50MHz. Here are my questions:

1. The ADC(external) is a simultaneous sampling ADC, which requires bunch of control signals to acquire data. I need to ensure that data is available to control model, every 50us (20KHz), I do not know how to fix the sampling time requrement for this model (ADC block) in simulink.
2. The code generator in simulink generates verilog code with clock as the input for the model. What is the difference between clock and sampling time? Should I connect this input to 50MHz?
3. Since ADC block is much faster than control block, should I use FIFO or rate transition block to synchronize them. Would it be necessary?
4. Can I just use one clock 50MHz, derive enable signals using counter and control the update rates of these two blocks? If yes how do do it in simulink?

Answer 1

[Rahul]

Hi @Gary,

The following points can be considered to resolve the questions mentioned:

• Since the control block runs at 20kHz (50µs), in order to synchronize data transfer the 'Sample Time' property of the ADC block will be required to be set at 50µs.

• The clock would refer to a continuous signal providing timing reference. The sampling time would signify the interval at which the system or block executes its logic. In the case of Verilog code generation the clock input is usually the operationg clock, hence this should be connected to 50MHz input.

• Since the sampling rates of the ADC and control block differ, it would make sense to use a Queue block with FIFO set or the Rate Transition block to align data transfer and achieve data synchronization.

• Yes, one clock of 50MHz can be used and enable signals can be derived using counters to control the update rates of the blocks. to implement a counter in Simulink, you can follow:

1. Use a Counter block to count clock cycles.
2. Use the Compare to Constant block to check when the counter reaches a specific value.
3. Use the output of the Compare block as an enable signal for your blocks.

The following MathWorks documentations can be referred:

'ADC block': https://www-test1.mathworks.com/help/releases/R2019a/supportpkg/texasinstrumentsc2000/ref/c280xc2833xadc.html

'Queue block': https://www-test1.mathworks.com/help/releases/R2019a/dsp/ref/queue.html

'Rate Transition block': https://www-test1.mathworks.com/help/releases/R2019a/simulink/slref/ratetransition.html

'Counter block': https://www-test1.mathworks.com/help/releases/R2019a/dsp/ref/counter.html

'Compare to Constant': https://www-test1.mathworks.com/help/releases/R2019a/simulink/slref/comparetoconstant.html

Thanks.