How to configure Kria KV260 Vision AI Starter Kit for FPGA-in-the-loop with Simulink?
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I would like to use HDL Verifier and the FPGA-in-the-loop with the Kria KV260 board.
In the "fpgaBoardManager" I created a custom board:
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1612726/image.png)
The Device Information should be corrected.
For FPGA Input Clock I'm trying to use an external pin such as PMOD but I get the error:
[Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM.
For this reason I was not able to Validate the board.
For FPGA in the loop I'd like to use JTAG:
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1612731/image.png)
To overcome this I tried another way.
I opened the Simulink example project "serial_lpf" and I followed the HDL Workflow Advisor to create FPGA in the loop project. The implementation failed for the same reason as above but it creates the project.
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1612736/image.png)
Knowing that the Kria is a System On Module and the clock is generated from MPSoC MultiProcessor, I opened the project with Vivado, I created the following design and I sucessfully generated the bitstream:
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1612741/image.png)
So the Simulink circuit receives the PS clock. I checked (using a counter) that the clock is generated as soon as the bit stream is loaded and without configures the PS part.
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1612746/image.png)
Simulink generates the co-simulation project and allows me to load bitstream to the FPGA with success. I see the clock (throught the counter) toggling.
But when I press Start for the simulation, I get the following error:
Error:Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.
I'm using Matlab 2023b and Vivado 2023.2.
Is possible to configure a PIN that not fail in FIL Test?
How can I solve the Did not receive version information from the hardware error?
Thanks
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Antworten (2)
Tom Richter
am 12 Feb. 2024
Hi Fabio,
I suggest contacting Technical Support to help you with this issue/question. If you go to https://www.mathworks.com/support/contact_us.html, you can submit a support request and add example or reproduction files. The page also displays phone contact information based on your location.
Best regards,
Tom
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