Matlab to RTL - Block RAM Enable

An array will get recognized as block RAM. So foo_ary(index) = write_value_at_index will write to the block RAM Question - how to use the enable of the block ram i.e. Above value should be written only when foo_ary_enable is '1'. So on certain index values the array should not be updated, what is the syntax for that? foo_ary_enable is calculated in another loop

Answer 1

[Girish Venkataramani]

Hi Arun,

I am from MathWorks. So, the example was written a while back. Many of the features were developed in later releases. The examples need to be updated - we have not yet done that.

Remember, if you want maximum efficiency (i.e., avoiding additional muxes etc), you should use the system object.

Answer 2

[Girish Venkataramani]

HDL Coder supports mapping to RAMs in two ways: 1. Manual mapping using the hdl.Ram system object 2. Automatic mapping from MATLAB code

If you know exactly how the RAM should be connected, it may be better to use the manual approach. When using the hdl.Ram system object, you must fully specify all the port connections, including read-address, write-address, write-data and write-enable. See the documentation for an example of using hdl.RAM, but the following is a snippet of usage:

persistent hRam; if isempty(hRam)

    hRam = hdl.RAM('RAMType', 'Dual port');

end

% execute single step of RAM

[~, ramRdDout] = step(hRam, ramWriteData, ramWriteAddr, ramWriteEnable, ramReadAddr);

However, you can also do this with the automatic approach. If you want to control using an enable line, all you may want to do is put it in a conditional:

if foo_ary_enable

   foo_ary(index) = write_value;

end

[Arun]

Girish, Thanks. Yes, with the automatic approach, surrounding the foo_ary(index) = write_value seems to be the right thing to do. However, in one of the mlhdlc_ examples (mlhdlc_heq.m) it is done as follows - if foo_ary_enable == '1'

write_value = my_new_write_value;

else

write_value = read_value

end And then outside the loop we have read_value = foo_ary(index); foo_ary(index) = write_value. The problem with doing it the recommended way (in the example), is that it would generate a mux at the input to the simple dual-port ram, the mux would select either the new value or the value read out of the ram. And the write_enable would not be used i.e. always enabled. The mux would add a delay which is not good.

Any thoughts on why the example code is written the way it is (perhaps someone from Mathworks could comment on this).

[krishna amar]

Hi, I am unable to gernerate the VHDL test bench for the example code given On RGB to YUV convertion. Mtlab is running for long time but I am not getting the Output. I have got the VHDL code but unable to generate Test bench.Please help me with this...................