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HDL Code Generation from Vision HDL Toolbox

What Is HDL Code Generation?

You can use MATLAB® and Simulink® for rapid prototyping of hardware designs. Vision HDL Toolbox™ blocks and System objects, when used with HDL Coder™, provide support for HDL code generation. HDL Coder tools generate target-independent synthesizable Verilog® and VHDL® code for FPGA programming or ASIC prototyping and design.

HDL Code Generation Support in Vision HDL Toolbox

Most blocks and objects in Vision HDL Toolbox support HDL code generation.

The following blocks and objects are for simulation only and are not supported for HDL code generation :

  • Frame To Pixels (visionhdl.FrameToPixels)

  • Pixels To Frame (visionhdl.PixelsToFrame)

  • FIL Frame To Pixels (visionhdl.FILFrameToPixels)

  • FIL Pixels To Frame (visionhdl.FILPixelsToFrame)

  • Measure Timing (visionhdl.MeasureTiming)

Streaming Pixel Interface in HDL

The streaming pixel bus and structure data type used by Vision HDL Toolbox blocks and System objects is flattened into separate signals in HDL.

In VHDL, the interface is declared as:

  PORT( clk             :   IN    std_logic;
        reset           :   IN    std_logic;
        enb             :   IN    std_logic;
        in0             :   IN    std_logic_vector(7 DOWNTO 0); -- uint8
        in1_hStart      :   IN    std_logic;
        in1_hEnd        :   IN    std_logic;
        in1_vStart      :   IN    std_logic;
        in1_vEnd        :   IN    std_logic;
        in1_valid       :   IN    std_logic;
        out0            :   OUT   std_logic_vector(7 DOWNTO 0); -- uint8
        out1_hStart     :   OUT   std_logic;
        out1_hEnd       :   OUT   std_logic;
        out1_vStart     :   OUT   std_logic;
        out1_vEnd       :   OUT   std_logic;
        out1_valid      :   OUT   std_logic

In Verilog, the interface is declared as:

  input   clk;
  input   reset;
  input   enb;
  input   [7:0] in0;  // uint8
  input   in1_hStart;
  input   in1_hEnd;
  input   in1_vStart;
  input   in1_vEnd;
  input   in1_valid;
  output  [7:0] out0;  // uint8
  output  out1_hStart;
  output  out1_hEnd;
  output  out1_vStart;
  output  out1_vEnd;
  output  out1_valid;