Hardware and Software Co-Design

Prototype algorithms on Zynq^® devices using HDL Coder™ and Embedded Coder^®

After you design and validate a pixel-streaming video processing algorithm in Simulink^®, you can target the design to the FPGA on the Zynq board, and generate embedded ARM^® code that interacts with the FPGA. You can route the video data to the ARM processor, and control AXI-Lite registers connected to the FPGA control logic.

Blocks

Video Capture (software interface)

Capture video to ARM processor on a Zynq-based video system that has an HDMI FMC card

Classes

visionzynq Connect to Zynq hardware

Functions

`changeFPGAImage`	Load image from on-board SD card into FPGA
`downloadImage`	Write image to on-board SD card and load into FPGA

Topics

Create Model Using Simulink Templates
Get started with a model configured for HDMI video processing.
Zynq Video Dataflow for HDMI Input
Learn about the video data path through the Zynq board when connected to an HDMI FMC card.
Zynq Video Dataflow for MIPI Input
Learn about the video data path through the Zynq board when connected to a MIPI^® FMC card.
Target FPGA on Zynq Hardware
FPGA targeting workflow using HDL Workflow Advisor.
Generate FPGA User Logic with AXI4-Stream Video Interface
This example shows how to select an AXI4-Stream Video interface for your generated FPGA user logic.
Target an ARM Processor on Zynq Hardware
Design and deploy algorithms to the ARM processor.
Models Generated from FPGA Targeting
Run Simulink models that interact with the deployed algorithms running on the FPGA.

Related Information

Hardware-Software Co-Design Workflow for SoC Platforms (HDL Coder)

Featured Examples

Lane Detection with Zynq-Based Hardware

Target a lane detection algorithm to the Zynq® hardware using the Vision HDL Toolbox™ Support Package for Xilinx® Zynq-Based Hardware.The inverse perspective mapping and lane-marking candidate extraction are targeted to the FPGA, and the ARM processor performs lane-fitting and overlay.

Open Example