Generate an IP Core for Zynq Platform from Simulink

Generate an IP Core

To generate a custom IP core to target the Xilinx^® ZC702, ZC706, or ZedBoard™:

1. Open the HDL Workflow Advisor.

2. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation.

   The coder automatically sets Synthesis tool to Xilinx Vivado, but you can change the Synthesis tool to Xilinx ISE.

3. For Target platform, select Xilinx Zynq ZC702 evaluation kit, Xilinx Zynq ZC706 evaluation kit, or Zedboard and click Run This Task.

   If you do not see your target hardware in the dropdown menu, select Get more to download the target support package.

   

4. In the Set Target > Set Target Interface task:

   • Reference design and Reference design path: If you have a downloaded reference design, select your Reference design. For Reference design path, enter the path to your downloaded reference design components.

   • Target Platform Interface: Select an interface for each port, then click Apply.

     You can map each DUT port to one of the following interfaces:

     • AXI4-Lite: Use this slave interface to access control registers or for lightweight data transfer. HDL Coder™ generates memory-mapped registers and allocates address offsets for the ports you map to this interface.

     • AXI4: Use this slave interface to connect to components that support burst data transmission. HDL Coder generates memory-mapped registers and allocates address offsets for the ports you map to this interface.

     • AXI4-Stream Video: Use this interface to send or receive a 32-bit scalar video data stream.

     • External Port: Use the external ports to connect to FPGA external IO pins, or to other IP cores with external ports.

       To connect to FPGA external IO pins, for Bit Range / Address / FPGA Pin, enter a cell array of pin names. If you do not enter pin names in a cell array format, the external ports are left unconnected in the embedded system tool project. For example, you can enter: {'Y10', 'A10', 'B10', 'D10'}.

     • A board-specific interface, such as LEDs General Purpose, DIP Switches, Push Buttons L-R-U-D-S, Pmod Connector JA1, Pmod Connector JB1, Pmod Connector JC1, or Pmod Connector JD1. Use these external ports to connect to external IO pins on the FPGA board.

       In the generated IP core, these ports are generic external ports. In a later step, if you use the HDL Workflow Advisor to integrate the generated IP core with embedded software in an embedded system tool project, the coder connects these ports to the board-specific FPGA pins.

   

5. In the HDL Code Generation > Generate RTL Code and IP Core task:

   • IP core folder: HDL Coder generates the IP core files in the output folder shown, including the HTML documentation.

   • IP repository: If you have an IP repository folder, enter its path manually or by using the Browse button. The coder copies the generated IP core into the IP repository folder.

   • Additional source files: If you are using a black box interface in your design to include existing Verilog^® or VHDL^® code, enter the file names. Enter each file name manually, separated with a semicolon (;), or by using the Add button. The source file language must match your target language.

   • Generate IP core report: Enable this option to generate HTML documentation for the IP core.

6. If you want to set options in the other HDL Workflow Advisor tasks, set them.

7. Right-click the HDL Code Generation > Generate RTL Code and IP Core task and select Run to Selected Task.

   To view the IP core report, click the link in the message window.

To learn more about custom IP core generation, see Custom IP Core Generation (HDL Coder).

Requirements and Limitations

To generate a custom IP core:

• The DUT must be an atomic system.

• There cannot be both an AXI4 interface and AXI4-Lite interface in the same IP core.

• The DUT cannot contain Xilinx System Generator blocks.

• If your target language is VHDL, and your synthesis tool is Xilinx ISE, the DUT cannot contain a model reference.

To map your DUT ports to an AXI4-Lite interface, the input and output ports must:

• Have a bit width less than or equal to 32 bits.

• Be scalar.

When mapping your DUT ports to an AXI4-Stream Video interface, the following requirements and limitations apply:

• Ports must have a 32-bit width.

• Ports must be scalar.

• The model must be single rate.

• You can have a maximum of one input video port and one output video port.

• Your synthesis tool must be Xilinx ISE.

The AXI4-Stream Video interface is not supported in Coprocessing – blocking processor/FPGA synchronization mode.