socIPCore

Create object to represent IP core running on FPGA board

Since R2019a

Description

The socIPCore object represents an active IP core on an FPGA board and provides read and write access to the IP.

Creation

Syntax

myCoreObj = socIPCore(axiMaster,IPCoreInfo,IPCoreName)

myCoreObj = socIPCore(axiMaster,IPCoreInfo,IPCoreName,Name,Value)

Description

myCoreObj = socIPCore(axiMaster,IPCoreInfo,IPCoreName) creates an socIPCore object that connects to an IP core running on an FPGA board. The object uses an socAXIMaster object to access memory locations in the IP core. IPCoreInfo is a structure generated when you run the SoC Builder tool and includes the board and IP core configuration parameters from your model.

You can create socIPCore objects representing any of these IPs:

• Traffic generator

• Performance monitor

• Direct memory access (DMA)

• Video DMA (VDMA)

• Video timing controller (VTC)

• VDMA trigger

• Frame buffer

• High definition multimedia interface (HDMI)

myCoreObj = socIPCore(axiMaster,IPCoreInfo,IPCoreName,Name,Value) sets properties using one or more name-value pairs. For example,

myIPobj=socIPCore(axiMaster, perf_mon,'PerformanceMonitor','Mode','Profile');

creates an socIPCore object that connects to an IP core on the specified board and sets the performance monitor mode to profile mode.

Input Arguments

axiMaster — Name of socAXIMaster object used for memory-mapped access

socAXIMaster object

Name of socAXIMaster object used for memory-mapped access, specified as an socAXIMaster object.

Create an socAXIMaster object using the socAXIMaster function, and use the created object as an input to socIPCore.

Example: mySocAXIObj = socAXIMaster('Xilinx'); myIPObj = socIPCore(mySocAXIObj,IPCoreInfo,'DMA')

IPCoreInfo — IP core information

structure

IP core information, specified as a structure generated by the SoC Builder tool. To access the structure, load the .mat file which is generated by SoC Builder tool. The file is named model_name_boardID_aximaster.mat. Loading the file will load the structures generated by the SoC Builder tool to your workspace.

The structures contain information for vendor IP and for user-specified IP which are specific to your model and board. The structures are named as follows:

• vdma_frame_buffer – A struct representing a frame buffer.

• perf_mon – A struct representing a performance monitor.

• vtc – A struct representing a video timing controller.

• vdma_hdmi_out – A struct representing a VDMA-based HDMI IP.

• atg – A struct representing an AXI traffic generator.

• DUT_ip – A struct representing a user IP named "DUT".

Note

The mat file loads additional structs for IPs, for internal access.

IPCoreName — IP core object type

'TrafficGenerator' | 'PerformanceMonitor' | 'VDMA' | 'DMA' | 'VDMATrigger' | 'VTC' | 'FrameBuffer' | 'HDMI'

IP core object type, specified as one of the values in this table:

Value	Description
'TrafficGenerator'	SoC Blockset™ memory traffic generator
'PerformanceMonitor'	SoC Blockset performance monitor
'VDMA'	Xilinx® VDMA IP
'DMA'	Analog Devices® DMA controller IP
'VTC'	Video timing controller
'VDMATrigger'	An IP used to trigger reading frames from the source (mm2s) VDMA
'FrameBuffer'	VDMA-based frame buffer IP
'HDMI'	VDMA-based HDMI IP

Data Types: string | character vector

Properties

PerfMonMode — Type of performance data to collect

'Profile' (default) | 'Trace'

Type of performance data to collect, specified as 'Profile' or 'Trace'. Specify 'Profile' mode to collect byte and burst counts for bandwidth and latency plots. 'Trace' mode to collect burst transaction event data for display as waveforms.

Object Functions

initialize	Initialize IP core corresponding to socIPCore object
start	Start IP core execution on hardware board

Version History

Introduced in R2019a