Hardware Implementation Pane

Hardware Implementation Pane Overview

Task Profiling in Simulation

ParameterDescriptionDefault Value
Show in SDI

Show task execution data collected in simulation in Simulation Data Inspector.

on
Save to file

Save task execution data to a file.

on
Overwrite file

Overwrite last task execution data file.

off

Task Profiling on Processor

ParameterDescriptionDefault Value
Show in SDIShow task execution data collected on hardware in Simulation Data Inspector.off
Save to fileSave task execution data to a file.off
Overwrite fileOverwrite last task execution data file.off
InstrumentationChoose to perform code instrumentation or kernel Instrumentation.Code

Operating System/Scheduler Settings

ParameterDescriptionDefault Value
Kernel Latency

Simulated kernel latency delay.

0

Task and memory simulation

ParameterDescriptionDefault Value
Set seed for simulating task duration and memory accessSet random number generator seed.off
Seed ValueSeed for the simulation of task duration deviation.

default

Cache input data at task startCache input data at task start.

off

Processor

ParameterDescriptionDefault Value
Number of coresSet the number of CPU cores in the processor.1

FPGA design (top-level)

ParameterDescriptionDefault Value
View/Edit Memory Map

Choose whether to perform global synthesis or per IP core synthesis.

Out of Context per IP

Include a JTAG master for host-based interaction

Use host-based scripts with an integrated JTAG master on the target platform.

on

Include processing system

For processor-based platforms, include the processing system.

on

Interrupt latency (s)

The latency from hardware asserting an interrupt to the start of the interrupt service routine.

0.00001

Register configuration clock frequency (MHz)

The system configuration clock drives the configuration register interfaces for the vendor IP cores in the system.

50

IP core clock frequency (MHz)

The clock for all Simulink® based generated HDL IP cores.

100

FPGA design (mem controllers)

ParameterDescriptionDefault Value
Controller clock frequency (MHz)

Frequency of datapath between memory interconnect and memory controller.

200

Controller data width (bits)

Bit width of datapath between memory interconnect and memory controller.

64

Bandwidth derating (%)

For every 100 clocks, will hold off all transaction execution for this number of clocks.

2.3

First write transfer latency (clocks)

Number of clock cycles between write request and start of transfer.

4

Last write transfer latency (clocks)

Number of clock cycles between the end of write transfer and completion of transaction.

4

First read transfer latency (clocks)

Number of clock cycles between read request and start of transfer.

5

Last read transfer latency (clocks)

Number of clock cycles between the end of read transfer and completion of transaction.

1

FPGA design (mem channels)

ParameterDescriptionDefault Value
Interconnect clock frequency (MHz)

Frequency of the master datapath to the interconnect controller in MHz.

200

Interconnect data width (bits)

Data width of master datapath to interconnect controller in bits.

64

Interconnect FIFO depth (num bursts)

Maximum number of bursts that can be buffered before data is dropped.

12

Interconnect almost-full depth

When the almost full depth is reached, the attached channel protocol interface block asserts back pressure to the data source.

8

FPGA design (debug)

ParameterDescriptionDefault Value
Memory channel diagnostic level

The internal operation of the memory channel can be instrumented for debug or diagnostic analysis.

Basic diagnostic signals

Include AXI interconnect monitor

Gather performance metrics of the memory interconnect such as data throughput, latency, and number of bursts executed.

off

Trace capture depthMaximum number of Trace entries to be logged in trace mode

1024