Validate Input and Output Port Signals Using Port Constraints
You can validate compile-time signal attributes on the input and output ports of a masked block by using port constraints. Compile-time signal attributes include data type, complexity, and dimensions. You can define the rules to validate the data types, the complexity (real or complex), and dimensions (scalar, vector, or 2-D matrix) of port signals. You can also add parameter conditions to the constraint. The port constraints are active on the associated port only when it satisfies all the parameter conditions. Port constraints allow you to check that signal attributes satisfy the specified rules without having to write validation code. The mask identifies each port with port identifiers. You associate the port constraint to a port identifier.
This example has a subsystem with two input ports and two output ports. The port constraints
mypc3 validate input and output signals.
Create Port Identifiers
First, create port identifiers to associate with the port constraint. To create port identifiers, right-click
subsys_mask > Edit Mask > Constraints > Port Identifiers. The Port Identifiers pane lists the port identifiers for the masked Subsystem block
Name: Enter the name for the port. This name uniquely identifies the port identifier in the mask. Multiple ports can have the same port identifier.
Type: Select the type of the port as either
Identifier Type: Select the type of identifier as
name if you want to identify the ports using names. Select
index, if you want to identify the ports using numbers.
Identifier(s): Enter the name of the port in case Identifier Type is
name. Each port name in a block is unique. Enter indices in case Identifier Type is
index. You can map multiple ports to one port identifier when the identifier type is
Note: If you select
name as the Identifier Type, then you do not need to select the
Type of port, because each port
name is unique.
Create Port Constraints
Next, create port constraints for the masked block. Create mask on the block. Go to Constraints > Port. The list of port constraints appears in the Constraint Browser.
Constraint Name: Enter the name for the constraint.
Associations: Select the port from the list. The list of port identifiers created appears here. You can select any port identifier to associate it with the constraint.
Rule: Set the rules for the constraint. You can set the permitted Data Types, Complexity, and Dimensions for the port values. When you set the Data Type as fixed point, you can also select the Signedness, Scaling, and Worlength.
Parameter Conditions: Set mask parameter conditions for the constraints. The port constraints are active on the associated port only when the port satisfies all the parameter conditions. To add parameter conditions in the Parameter Conditions section, click Add. In Parameter Name, select the parameter name. In Parameter Values, specify the permitted values as comma-separated list.
Diagnostic Level: If the port constraint is not satisfied, you can display an error or a warning message during compile time. Select
Diagnostic Message: You can specify an error or a warning message that will be displayed if the port constraint validation fails.
Validate Port Constraints
Simulate the model. During the compilation stage, the compile process validates specified port constraints for the associated port. If the port constraint validation fails, then the error or warning message entered in the port constraint is displayed in the Diagnostic Viewer.
=== Simulation (Elapsed: 3 sec) === Error:Data at 'Input Port 1' of block 'slexMaskPortConstraints/subsys_mask' is invalid. Caused by: Expected data types for the port must be double. However, the port data type is single. 'To meet constraints of the mask'. Error:An error occurred while propagating data type 'single' from 'slexMaskPortConstraints/In4', output port 1.