Choose Between Frame Mode and Sample Mode
R2026bThe HDL Cosimulation block operates in sample mode or frame mode. In sample mode, the block transmits one sample per time step between Simulink® and the HDL simulator. In frame mode, the block transmits a frame of multiple consecutive samples per time step. This table lists which mode to use based on your design and goals:
| When to Use Sample Mode | When to Use Frame Mode |
|---|---|
| Your model processes one sample at a time. | Your model processes streaming data in frames. |
| You need cycle-accurate interaction between Simulink and the HDL simulator. | You want to reduce the number of Simulink-to-HDL communication cycles. |
| Your design has control-path logic that depends on per-sample feedback. | You want to improve cosimulation speed. |
Frame and Sample Mode Signal Mapping
You cannot set the HDL Cosimulation block to frame or sample mode directly. Instead, the block determines which mode to use based on the dimensions of the Simulink signal connected to the block.
Frame Mode
Frame mode is supported only for scalar HDL ports. The HDL Cosimulation block uses frame mode if:
You connect an N-by-1 column vector or 1-D vector signal to a scalar HDL port. The block interprets the signal as a frame of N samples.
You connect an M-by-N matrix signal to the block, and the HDL port width exceeds 128 bits. The block interprets the signal as a frame of M samples.
All input ports must share the same frame size, and the same mode (frame or sample mode).
To force the block to use sample mode, convert your Simulink signal:
If the HDL block port has a width equal to or less than 128 bits, use a 1-by-1 scalar.
If the HDL block port has a width greater than 128 bits, use a 1-by-M row vector.
Sample Mode
The HDL Cosimulation block uses sample mode if:
The signal is a 1-by-1 scalar. The block maps this signal to a scalar in the HDL port.
The signal is an N-by-1 vector. The block maps this signal to a vector of size N in the HDL port.
The signal is a 1-by-M row vector. The block maps this signal to a scalar, wide HDL port that has a width equal to M multiplied by the data width of the Simulink signal. For example: a scalar 256 HDL port can be mapped to a Simulink 1-by-8 vector of
uint32.
For more information about frame mode, see Frame-Based HDL Cosimulation. For details on the supported data types for each mode, see Supported Data Types.
Note
The block always treats SystemVerilog packed arrays as scalar HDL ports. For example, the block treats this HDL input definition as a 32-bit scalar:
input logic[7:0][3:0] in1
