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Create Hardware Design Patterns Using the MATLAB Function Block For HDL Code Generation

You can use the HDL design patterns library em_hdl_design_patterns to implement patterns that use the MATLAB Function block to solve common hardware modeling problems. For more information on the em_hdl_design_patterns library, see MATLAB Function Block Design Patterns for HDL.

HDL Coder™ supports a subset of MATLAB Function block features that you can use in HDL implementations of various digital signal processing (DSP) and telecommunication applications, such as sequence detectors, pattern generators, encoders, and decoders. Some of the features supported by the MATLAB Function block in HDL Coder are:

  • Numeric classes, including int, uint, logical, single, and double

  • Fixed-point arithmetic using the fi object

  • Arithmetic, logical, relational, and bitwise operator support

  • MATLAB® expressions that use the preceding operators

  • 1-D and 2-D matrix operations

  • Matrix subscripting

  • Control flow using if, switch, and for statements

  • Subfunctions

  • Persistent variables that model state

  • Fixed point and integer MATLAB library functions

Open the Pattern Library

The MATLAB Function block expresses algorithm behavior in a concise and textual way, which enables you to model hardware algorithms at a high level. You can use HDL Coder to implement these MATLAB Function block hardware-friendly algorithms. The sample patterns library em_hdl_design_patterns shows how to model common, HDL-supported hardware modeling constructs using MATLAB Function blocks. Open this sample library model at the MATLAB command prompt by entering:


Model Arithmetic Expressions Using MATLAB Function Blocks

In the em_hdl_design_patterns library, you can use the blocks in the Adders and Misc subsystems to model arithmetic expressions. To model arbitrary length arithmetic operations using signed and unsigned logic vectors, use the fi object. When using fi objects in a MATLAB Function block, the fi function helps you to define a fixed-point object with a customized numerictype object and fimath object. The numerictype object defines the sign, word length, and fraction length attributes of the fi object and the fimath object defines rounding and saturation modes. For more information, see fi. To generate HDL code using the fi function, use these fimath settings:

  'RoundMode', 'floor',...
  'OverflowMode', 'wrap',...
  'ProductMode', 'FullPrecision', 'ProductWordLength', 32,...
  'SumMode', 'FullPrecision', 'SumWordLength', 32);

When modeling algorithms that require more complicated rounding and saturation logic, you can use other fimath modes for rounding, such as floor, ceil, fix, or nearest, and overflow, such as wrap, or saturate.

To see the affect of fimath properties on generated HDL code, generate HDL code for eml_hdl_design_patterns/Adders/add_with_carry and eml_hdl_design_patterns/Misc/eml_expr.

Model Combinatorics Using Fixed-Point Algorithms

Open the eml_hdl_design_patterns library and select the Combinatorics/eml_expr block. The eml_expr MATLAB Function block implements a simple expression that contains addition, subtraction, and multiplication operators with different fixed-point data types. Generate HDL code for the MATLAB Function block by following the process in Generate HDL Code from a MATLAB Function Block.

This is the generated VHDL code:

   --MATLAB Function 'Subsystem/eml_expr': '<S2>:1'
   -- fixpt arithmetic expression
   mul_temp <= signed(a) * signed(b);
   sub_cast <= resize(mul_temp, 11);
   add_cast <= resize(signed(a & '0'), 7);
   add_cast_0 <= resize(signed(b), 7);
   add_temp <= add_cast + add_cast_0;
   sub_cast_0 <= resize(add_temp & '0' & '0', 11);
   expr <= sub_cast - sub_cast_0;
   -- cast the result to correct output type
   y <= "0111111" WHEN ((expr(10) = '0') AND (expr(9 DOWNTO 7) /= "000"))
           OR ((expr(10) = '0') AND (expr(7 DOWNTO 1) = "0111111"))
         "1000000" WHEN (expr(10) = '1') AND (expr(9 DOWNTO 7) /= "111")
          std_logic_vector(expr(7 DOWNTO 1) + ("0" & expr(0)));

This is the generated Verilog code from the eml_expr MATLAB Function block:

//MATLAB Function 'Subsystem/eml_expr': '<S2>:1'
   // fixpt arithmetic expression
   assign mul_temp = a * b;
   assign sub_cast = mul_temp;
   assign add_cast = {a[4], {a, 1'b0}};
   assign add_cast_0 = b;
   assign add_temp = add_cast + add_cast_0;
   assign sub_cast_0 = {{2{add_temp[6]}}, {add_temp, 2'b00}};
   assign expr = sub_cast - sub_cast_0;
   // cast the result to correct output type
   assign y = (((expr[10] == 0) && (expr[9:7] != 0))
             || ((expr[10] == 0) && (expr[7:1] == 63)) ? 7'sb0111111 :
             ((expr[10] == 1) && (expr[9:7] != 7) ? 7'sb1000000 :
             expr[7:1] + $signed({1'b0, expr[0]})));

The generated HDL code shows the conversion of this expression with fixed-point operands. The default fimath specification for the blocks determines the behavior of arithmetic expressions using fixed-point operands inside the MATLAB Function block. You can see the fimath settings in the block comments of the eml_expr block.

Model State Using Persistent Variables

To model complex control logic, your model must be able to model registers. When generating code, you can represent state-holding elements as persistent variables. A persistent variable retains its value across function calls in the MATLAB code and across sample times steps during simulation. State-holding elements in hardware such as registers and flip-flops have similar behavior. Consequently, persistent variables in MATLAB Function blocks map to registers in hardware.

The Delays subsystem in the em_hdl_design_patterns library contains MATLAB Function blocks that show how you can use global and local reset conditions to change the values of persistent variables and how you can use vectors of persistent variables to model integer delay, tap delay, and tap delay vector blocks. You can use these design patterns to implement sequential algorithms that carry state between executions of the MATLAB Function block in a model.

Note that the MATLAB code must read the persistent variable before it is written in order for HDL Coder to map the persistent variable to a register in the HDL code. When generating code, HDL Coder displays a warning message if the MATLAB code does not follow this convention.

Model Control Logic and Finite State Machines

You can use conditional statements such as switch, case, if, and else together with fixed-point arithmetic operations and delay elements to model control logic. In the em_hdl_design_patterns library, the MATLAB Function blocks in the FSMs subsystems show how to use these conditional statements. The mealy_fsm_blk and moore_fsm_blk blocks provide example implementations of Mealy and Moore finite state machines in a MATLAB Function block.

The MATLAB Function block can model simple state machines and other control-based hardware algorithms, such as pattern matchers or synchronization-related controllers, by using control statements and persistent variables. For modeling more complex and hierarchical state machines with complicated temporal logic, use a Stateflow® chart to model the state machine.

Model Counters

The MATLAB Function blocks in the Counters subsystem show how to model state and quantize data elements in loops. You can use counters for global reset control of persistent state variables and local reset control. To implement arithmetic and control logic algorithms in MATLAB Function blocks intended for HDL code generation, ensure that:

  • The top-level MATLAB Function block is called once per time step.

  • It is possible to fully unroll program loops.

  • Persistent variables with reset values and update logic are used to hold values across simulation time steps.

  • Quantized data variables are used inside loops.

Model Bitwise and Bit Conversion Operations

The MATLAB Function block supports a variety of bitwise operations useful for hardware bit manipulation operations, such as bits-to-integer conversion, integer-to-bits conversion, bit concatenation, bit packing and unpacking, and pn-sequence generation and bit-scramblers.

These bitwise functions are supported by HDL Coder:

  • bitget, bitsliceget, bitconcat, bitset, bitcmp

  • bitand, bitor, bitxor

  • bitandreduce, bitorreduce, bitxorreduce

  • bitshift, bitsll, bitsrl, bitsra, bitrol, bitror

When modeling pure logic and no math operations in the MATLAB Function block, use:

  • Unsigned instead of signed input operands.

  • Non-saturating fimath options to generate less hardware.

  • wrap as the OverflowMode setting.

  • floor as the RoundMode setting.

In the em_hdl_design_patterns library, the MATLAB Function block hdl_bit_ops in the Bit Twiddlers subsystem and the signal_distance and nibble_swap_with_slice_concat MATLAB Function blocks in the Word Twiddlers subsystem show how to apply these settings.

For an example model that shows how you can perform a conversion from integer-to-bits and bits-to-integer, open the model hdlcoder_int2bits_bits2int, by entering:


You can also open the model by double-clicking on the black text box hdlcoder_int2bits_bits2int in the Word Twiddlers subsystem.

The hdlcoder_int2bits_bits2int model uses these MATLAB Function blocks from the Word Twiddlers subsystem in the em_hdl_design_patterns library:

  • Bits2Int

  • Int2Bits

  • Integer to Bits

  • Bits to Integer

Model Hardware Elements

You can use the MATLAB Function block to model various hardware elements like barrel shifters, rotators, and carry-save adders by using MATLAB scripts. In the em_hdl_design_patterns library, see the Shift Registers subsystem for MATLAB Function blocks that model various shift register hardware elements, such as 32-bit and 64-bit shift registers.

See Also

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