Main Content

Generate FPGA Block RAM from Lookup Tables

You can follow these guidelines to learn about how you can map the lookup table blocks to RAM to save area on the target FPGA device.

Each guideline has a severity level that indicates the level of compliance requirements. To learn more, see HDL Modeling Guidelines Severity Levels.

Guideline ID

2.3.1

Severity

Strongly Recommended

Description

To map lookup tables to a block RAM, you can use the adaptive pipelining optimization. This optimization is disabled by default. The optimization inserts a Delay block that has a Delay length of 1 and ResetType set to none immediately following the Lookup Table block. This modeling pattern efficiently maps your design to a Block RAM on the FPGA. To use the adaptive pipelining optimization, you must:

  • Make sure that AdaptivePipelining is enabled on the model.

  • Specify the synthesis tool.

To learn more about adaptive pipelining, see Adaptive Pipelining.

If you do not want to use the adaptive pipelining optimization for the entire design, you can selectively enable this optimization for certain Subsystems in your design, or create the same modeling pattern in your design that is otherwise generated by the optimization.

For an example, open the model hdlcoder_LUT_BRAM_mapping.slx.

open_system('hdlcoder_LUT_BRAM_mapping')
set_param('hdlcoder_LUT_BRAM_mapping','SimulationCommand','Update')

The adaptive pipelining optimization is disabled on this model.

hdlget_param('hdlcoder_LUT_BRAM_mapping','AdaptivePipelining')
ans =

    'off'

The LUT_BRAM Subsystem contains a 1-D Lookup Table block followed by a Delay block that has a Delay length of 1 and ResetType set to none.

open_system('hdlcoder_LUT_BRAM_mapping/LUT_BRAM')

When you generate HDL code and synthesize the design on an FPGA, it efficiently maps to Block RAM. This figure displays the synthesis results for the LUT_BRAM Subsystem.

The LUT Subsystem in this model does not use this modeling pattern.

open_system('hdlcoder_LUT_BRAM_mapping/LUT')

As adaptive pipelining is disabled on the model, synthesizing this Subsystem maps the logic to LUTs instead of utilizing the Block RAMs. This figure displays the synthesis results for the LUT Subsystem.

See Also

Functions

Simulink Configuration Parameters

Related Topics