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Estimate Achievable Target Frequency Without Running Synthesis

By using the Simscape HDL Workflow Advisor, you can estimate the optimal frequency that you want your Simscape™ models to achieve on FPGA without running synthesis. This method of estimation helps you to run the model on the hardware without any mismatches and provides information about whether the Simscape model can achieve the required time step on FPGA without running synthesis.

The estimation is based on the Sample time parameter you specify in the Solver Configuration (Simscape) block of your model. If the calculated FPGA sample time matches the specified sample time, the Advisor automatically sets Target Frequency (MHz) in the Configuration Parameters dialog box and treats the model rates as hardware rates. However, if the FPGA sample time does not match the specified sample time, the Advisor displays a warning message for the generated HDL implementation model.

The estimation is limited to Simscape models containing a single Simscape network.

Example Models with Estimated Sample Time

The table lists the Simscape Hardware-in-the-Loop (HIL) example models with their respective estimated sample times on a Windows® 11 Intel® Xeon® W-2133 CPU @3.60GHz test system with target device family set to Xilinx® Vivado® Virtex® 7.

ExampleRequired Sample Time (μs)Estimated Achievable Sample Time (μs)True FPGA Sample Time (μs)
Half-wave rectifier10.150.116
Buck converter10.580.49
Boost converter11.040.493
Bridge rectifier100.6940.38
DC motor10001.0110.9636

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