Design Considerations for RAM Blocks and Blocks in HDL Operations Library

Follow these guidelines to learn how you can use RAM blocks and blocks in the HDL Operations library when modeling your design.

Each guideline has a severity level that indicates the level of compliance requirements. To learn more, see HDL Modeling Guidelines Severity Levels.

RAM Block Access Considerations

Guideline ID

2.1.1

Severity

Recommended

Description

In the HDL RAMs block library, there are seven different RAM blocks and a HDL FIFO block. If you see a RAM block that has the term System as part of the block name, such as Single Port RAM System, it is recommended that you use this block instead of the equivalent block that does not have System as part of the name, such as Single Port RAM. These blocks have System as part of the name because the block implementation is based on the hdl.RAM System object™. The system blocks support vector inputs and yield much faster simulation results when used in your Simulink^® model.

When you use these blocks, make sure that the input sample time and output sample time are the same. This table illustrates the various RAM blocks that you can use and their purpose. The generated HDL code for these blocks maps to RAM in most FPGAs.

Block Name	Recommended Usage
Single Port RAM System	Use this block to replace the Single Port RAM block in your model. You obtain faster simulation results when using this block in your model. The block implementation uses a MATLAB System block that uses the hdl.RAM System object. Use this block to perform sequential read and write operations. In the Block Parameters dialog box of the block, you can specify an initial value for the RAM. To perform simultaneous read and write operations to different addresses, use the Simple Dual Port RAM System or the Dual Port RAM System block instead. The block does not support boolean inputs. Cast boolean types to ufix1 for input to the block.
Simple Dual Port RAM System	Use this block to replace the Simple Dual Port RAM block in your model. You obtain faster simulation results when using this block in your model. The block implementation uses a MATLAB System block that uses the hdl.RAM System object. Use this block to perform simultaneous read and write operations. It has a single output port to read data. In the Block Parameters dialog box of the block, you can specify an initial value for the RAM. The block does not support boolean inputs. Cast boolean types to ufix1 for input to the block.
Dual Port RAM System	Use this block to replace the Dual Port RAM block in your model. You obtain faster simulation results when using this block in your model. The block implementation uses a MATLAB System block that uses the hdl.RAM System object. Use this block to perform simultaneous read and write operations. It has a read data output port and a write data output port. In the Block Parameters dialog box of the block, you can specify an initial value for the RAM. If you do not want to use the write data output port, to achieve better RAM inference, use the Simple Dual Port RAM System block instead. The block does not support boolean inputs. Cast boolean types to ufix1 for input to the block.
True Dual Port RAM System	The block implementation uses a MATLAB System block that uses the hdl.RAM System object. Use this block to perform simultaneous read and write operations. It has two write data output ports and each write port also performs a read operation. In the Block Parameters dialog box of the block, you can specify an initial value for the RAM. The block does not support boolean inputs. Cast boolean types to ufix1 for input to the block.
Simple Tri Port RAM System	The block implementation uses a MATLAB System block that uses the hdl.RAM System object. Use this block to perform simultaneous read and write operations. It has two output ports to read data. In the Block Parameters dialog box of the block, you can specify an initial value for the RAM. The block does not support boolean inputs. Cast boolean types to ufix1 for input to the block.
Dual Rate Dual Port RAM	This block does not have an equivalent System object-based implementation. Use this block to perform simultaneous read and write operations to two different addresses that operate at different clock rates. You cannot perform concurrent access to the same address of the RAM. To run the RAM ports at multiple clock rates, set Clock Inputs to Multiple. You can access this RAM twice in one clock cycle.
HDL FIFO	The HDL FIFO block stores a sequence of samples in a first in, first out (FIFO) register. The inputs, In and Push, and the outputs, Out and Pop can run at different sample times. Specify the ratio of output to input sample time as a positive integer or 1/N such that N is a positive integer. For example: If you specify the ratio as 2, the output sample time is twice the input sample time. The outputs run slower than the input. If you specify the ratio as 1/2, the output sample time is half the input sample time. The outputs run faster than the input. The signals Full, Empty, and Num run at the fastest rate in your model. When you use the control output of the FIFO in an input, you may have to perform to a rate transition. The input and output rates of the FIFO block are synchronous to each other.

Serial to Parallel Conversion

Guideline ID

2.1.2

Severity

Informative

Description

You can use the Serializer1D and Deserializer1D blocks to perform serial to parallel and parallel to serial conversion.