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Simulate and Generate HDL Code for Tapped Delay Enabled Resettable Synchronous Block

This example shows how to implement the Tapped Delay Enabled Resettable Synchronous block in a Simulink® model that a delays scalar signal multiple sample periods and output all delayed versions when external Enable signal is true and external Reset signal is false. You also generate HDL code for the model.

Open and Load Model

Load and open the TappedDelayEnableResetModel model. The DUT subsystem contains a Tapped Delay Enabled Resettable Synchronous block. The Number of delay parameter corresponds to the number of delayed versions of the input signal the block returns.


Simulate Design

Simulate the TappedDelayEnableResetModel model. The output of the block is a vector. The block returns four signals, the first delayed by four sample periods, the second delayed by three, and so on.


Generate HDL code

You can generate the HDL code for a model by using HDL Coder™. Generate the HDL code for DUT subsystem using the makehdl function.