FPGA Data Capture
Capture raw data using FPGA input and output (IO) application programming interface (API) from an RFSoC device. Configure an SoC model for the HDL code generation by using the HDL Workflow Advisor. Generate the HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB® script to interactively capture data from the deployed HDL design.
Topics
- ARM Targeting
Design and deploy algorithms to the ARM® processor.
- Reference Designs for RFSoC Devices
Learn about how to use RFSoC reference designs and their requirements.
Featured Examples
DAC and ADC Data Loopback on RFSoC Device
Capture raw analog-to-digital converter (ADC) data using the FPGA I/O API from the AMD® Zynq® UltraScale+™ RFSoC ZCU111, ZCU208, ZCU216, or DFE ZCU670 evaluation kit. This example uses the HDL Workflow Advisor to configure an SoC model for HDL code generation. In this example, you generate the HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB® script to interactively capture data from the deployed HDL design.
RF Data Converter IQ Mixer Mode on RFSoC Device
Enable the RFSoC built-in numerically-controlled oscillator (NCO) mixer. The mixer design uses a different data format that, instead of providing real signals, provides a complex in-phase and quadrature (IQ) signal to a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC). There is more data to transfer to direct memory access (DMA) and back to MATLAB® given that you need to transfer I and Q samples back. You can accommodate this larger data width by increasing the DMA data width to 128 bits.
