Supported Networks, Boards, and Tools
Supported Pretrained Networks
Deep Learning HDL Toolbox™ supports code generation for series convolutional neural networks (CNNs or ConvNets). You can generate code for any trained CNN whose computational layers are supported for code generation. For a full list, see Supported Layers. You can use one of the pretrained networks listed in the table to generate code for your target Intel® or Xilinx® FPGA boards.
| Network | Network Description | Type | Single Data Type (with Shipping Bitstreams) | INT8 data type (with Shipping Bitstreams) | Application Area | ||||
| ZCU102 | ZC706 | Arria10 SoC | ZCU102 | ZC706 | Arria10 SoC | Classification | |||
| AlexNet | AlexNet convolutional neural network. | Series Network | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | Classification |
| LogoNet | Logo recognition network (LogoNet) is a MATLAB® developed logo identification network. For more information, see Logo Recognition Network. | Series Network | Yes | Yes | Yes | Yes | Yes | Yes | Classification |
| DigitsNet | Digit classification network. See Create Simple Deep Learning Neural Network for Classification. | Series Network | Yes | Yes | Yes | Yes | Yes | Yes | Classification |
| Lane detection | LaneNet convolutional neural network. For more information, see Deploy Transfer Learning Network for Lane Detection. | Series Network | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | Classification |
| VGG-16 | VGG-16 convolutional neural network. For the pretrained VGG-16 model, see
| Series Network | No. Network exceeds PL DDR memory size. | No. Network exceeds FC module memory size. | Yes | Yes | No. Network exceeds FC module memory size. | Yes | Classification |
| VGG-19 | VGG-19 convolutional neural network. For the pretrained VGG-19 model, see
| Series Network | No. Network exceeds PL DDR memory size. | No. Network exceeds FC module memory size. | Yes | Yes | No. Network exceeds FC module memory size. | Yes | Classification |
| Darknet-19 | Darknet-19 convolutional neural network. For the pretrained darknet-19
model, see | Series Network | Yes | Yes | Yes | Yes | Yes | Yes | Classification |
| Radar Classification | Convolutional neural network that uses micro-Doppler signatures to identify and classify the object. For more information, see Bicyclist and Pedestrian Classification by Using FPGA. | Series Network | Yes | Yes | Yes | Yes | Yes | Yes | Classification and Software Defined Radio (SDR) |
Defect Detection snet_defnet | snet_defnet is a custom AlexNet network used to identify and
classify defects. For more information, see Defect Detection. | Series Network | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | Classification |
Defect Detection snet_blemdetnet | snet_blemdetnet is a custom convolutional neural network
used to identify and classify defects. For more information, see Defect Detection. | Series Network | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | Classification |
| DarkNet-53 | Darknet-53 convolutional neural network. For the pretrained DarkNet-53 model,
see darknet53. | Directed acyclic graph (DAG) network based | Yes | Yes | Yes | Yes | Yes | No | Classification |
| ResNet-18 | ResNet-18 convolutional neural network. For the pretrained ResNet-18 model, see
resnet18. | Directed acyclic graph (DAG) network based | Yes | Yes | Yes | Yes | Yes | Yes | Classification |
| ResNet-50 | ResNet-50 convolutional neural network. For the pretrained ResNet-50 model, see
resnet50. | Directed acyclic graph (DAG) network based | No. Network exceeds PL DDR memory size. | No. Network exceeds PL DDR memory size. | Yes | Yes | Yes | Yes | Classification |
| ResNet-based YOLO v2 | You only look once (YOLO) is an object detector that decodes the predictions from a convolutional neural network and generates bounding boxes around the objects. For more information, see Vehicle Detection Using ResNet-18 Based YOLO v2 Deployed to FPGA. | Directed acyclic graph (DAG) network based | Yes | Yes | Yes | Yes | Yes | Yes | Object detection |
| MobileNetV2 | MobileNet-v2 convolutional neural network. For the pretrained MobileNet-v2
model, see mobilenetv2. | Directed acyclic graph (DAG) network based | Yes | Yes | Yes | Yes | Yes | Yes | Classification |
| GoogLeNet | GoogLeNet convolutional neural network. For the pretrained GoogLeNet model, see
googlenet. | Directed acyclic graph (DAG) network based | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | No. To use the bitstream, enable the LRNBlockGeneration
property of the processor configuration for the bitstream and generate the bitstream
again. | Classification |
| PoseNet | Human pose estimation network. | Directed acyclic graph (DAG) network based | Yes. | Yes | Yes | Yes | Yes | Yes | Segmentation |
| U-Net | U-Net convolutional neural network designed for semantic image segmentation. | Directed acyclic graph (DAG) network based | No. PL DDR memory oversize. | No. PL DDR memory oversize. | No. PL DDR memory oversize. | No. PL DDR memory oversize. | No. PL DDR memory oversize. | Yes | Segmentation |
| SqueezeNet-based YOLO v3 | The you-only-look-once (YOLO) v3 object detector is a multi-scale object detection network that uses a feature extraction network and multiple detection heads to make predictions at multiple scales. | dlnetwork object | Yes | Yes | No | No | No | No | Object detection |
| Sequence-to-sequence classification | Classify each time step of sequence data using a long short-term memory (LSTM) network. See Run Sequence-to-Sequence Classification on Intel FPGA. | Long short-term memory (LSTM) network | Yes | Yes | Yes | No | No | No | Sequence data classification |
| Time series forecasting | Forecast time series data using a long short-term memory (LSTM) network. See Run Sequence Forecasting on FPGA by Using Deep Learning HDL Toolbox. | Long short-term memory (LSTM) network | Yes | Yes | Yes | No | No | No | Forecast time series data |
| Word-by-word text generation | Generate text word-by-word by using a long short-term memory (LSTM) network. See Generate Word-by-Word Text on FPGAs by Using Deep Learning HDL Toolbox. | Long short-term memory (LSTM) network | Yes | Yes | Yes | No | No | No | Sequence data prediction |
| YAMNet | Pretrained audio classification network. See yamnet (Audio Toolbox) and Deploy YAMNet Networks to FPGAs with and without Cross-Layer Equalization. | Series Network | Yes | Yes | Yes | Yes | Yes | Yes | Audio data classification |
| Semantic Segmentation Using Dilated Convolutions | Semantic segmentation using dilated convolution layer to increase coverage area without increasing the number of computational parameters. See Deploy Semantic Segmentation Network Using Dilated Convolutions on FPGA. | Series Network | Yes | Yes | Yes | Yes | Yes | Yes | Segmentation |
| Time series forecasting | Forecast time series data using a long short-term memory (LSTM) network. See Run Sequence Forecasting Using a GRU Layer on an FPGA. | Gated recurrent unit (GRU) layer network | Yes | Yes | Yes | No | No | No | Forecast time series data |
| Pruned image classification network | Pruned image classification network. See Deploy Image Recognition Network on FPGA with and Without Pruning. | Series network | Yes | Yes | Yes | Yes | Yes | Yes | Image classification |
| Very-deep super-resolution (VDSR) network | Create high resolution images from low-resolution images by using VDSR networks. See Increase Image Resolution Using VDSR Network Running on FPGA. | Series network | Yes | Yes | Yes | Yes | Yes | Yes | Image processing |
| YOLO v4 tiny | The you only look once version 4 (YOLO v4) object detection network is a one-stage object detection network and is composed of three parts: backbone, neck, and head. See Detect Objects Using YOLOv4-tiny Network Deployed to FPGA. | dlnetwork object | Yes | Yes | Yes | Yes | Yes | Yes | Object detection |
Supported Boards
These boards are supported by Deep Learning HDL Toolbox:
Xilinx Zynq®-7000 ZC706
Intel Arria® 10 SoC
Xilinx Zynq UltraScale+™ MPSoC ZCU102
Custom boards. For more information, see Deep Learning Processor IP Core Generation for Custom Board.
Third-Party Synthesis Tools and Version Support
Deep Learning HDL Toolbox has been tested with:
AMD® Vivado® Design Suite 2024.1
Intel Quartus® Prime Standard 22.1.1
